| Age | Commit message (Expand) | Author |
|---|
| 2025-11-22 | [RISCV] Support zilsd-4byte-align for i64 load/store in SelectionDAG. (#169182) | Craig Topper |
| 2025-11-21 | [RISCV] Incorporate scalar addends to extend vector multiply accumulate chain... | Ryan Buchner |
| 2025-11-20 | [RISCV][llvm] Select splat_vector(constant) with PLI (#168204) | Brandon Wu |
| 2025-11-19 | [RISCV][DAGCombiner] Fix potential missed combine in VL->VW extension (#168026) | Kai Lin |
| 2025-11-19 | CodeGen: Add subtarget to TargetLoweringBase constructor (#168620) | Matt Arsenault |
| 2025-11-18 | [RISCV] Legalize misaligned unmasked vp.load/vp.store to vle8/vse8. (#167745) | Craig Topper |
| 2025-11-18 | [RISCV] Remove unused argument check (NFC) (#168313) | Garth Lei |
| 2025-11-17 | [RISCV] Fold Zba-expanded (mul (shr exact X, C1), C2) (#168019) | Piotr Fusik |
| 2025-11-17 | [llvm][RISCV] Support splat and vp_splat for zvfbfa codegen (#167920) | Brandon Wu |
| 2025-11-17 | [VP][RISCV] Enable promotion on fixed-length vp intrinsics with zvfbfmin (#16... | Brandon Wu |
| 2025-11-13 | [RISCV] For (2^N +/- 2^M) muls, prefer ADD to SUB (#166757) | Piotr Fusik |
| 2025-11-14 | [RISCV][llvm] Handle INSERT_VECTOR_ELT, EXTRACT_VECTOR_ELT codegen for zvfbfa... | Brandon Wu |
| 2025-11-12 | [RISCV][GISel] Fallback to SelectionDAG for vleff intrinsics. (#167776) | Craig Topper |
| 2025-11-12 | [RISCV] Remove custom legalization of v2i16/v4i8 loads for P extension. (#167... | Craig Topper |
| 2025-11-12 | [RISCV] Expand multiplication by `2^N * 3/5/9 + 1` with SHL_ADD (#166933) | Piotr Fusik |
| 2025-11-11 | [RISCV][llvm] Preliminary P extension codegen support (#162668) | Brandon Wu |
| 2025-11-10 | CodeGen: Remove TRI arguments from stack load/store hooks (#158240) | Matt Arsenault |
| 2025-11-10 | [llvm][RISCV] Support Zvfbfa codegen for fneg, fabs and copysign (#166944) | Brandon Wu |
| 2025-11-06 | [RISCV] Optimize (and (icmp x, 0, neq), (icmp y, 0, neq)) utilizing zicond ex... | Ryan Buchner |
| 2025-11-07 | [RISCV] Use SLLI.UW in double-SHL_ADD multiplications (#166728) | Piotr Fusik |
| 2025-11-06 | [RISCV] More explicitly check that combineOp_VLToVWOp_VL removes the extends ... | Craig Topper |
| 2025-11-06 | [RISCV] Expand multiplication by `(2/4/8 * 3/5/9 + 1) << N` with SHL_ADD (#16... | Piotr Fusik |
| 2025-11-05 | [RISCV] Implement shouldFoldMaskToVariableShiftPair (#166159) | Sudharsan Veeravalli |
| 2025-11-04 | [RISCV] Use TargetConstant for the immediate RISCVISD::SHL_ADD nodes. (#166312) | Craig Topper |
| 2025-11-04 | [RISCV][NFC] Match `3/5/9 * 3/5/9 * 2^N` without a loop (#165547) | Piotr Fusik |
| 2025-11-02 | [ADT] Prepare to deprecate variadic `StringSwitch::Cases`. NFC. (#166020) | Jakub Kuderski |
| 2025-10-31 | [RISCV] Fix misuse of EVT::changeVectorElementType() in legalizeScatterGather... | Craig Topper |
| 2025-10-30 | [RISCV] Support P extension ABSW instruction. (#165047) | Craig Topper |
| 2025-10-24 | [RISCV] Support codegen for some scalar P extension instructions. (#164359) | Craig Topper |
| 2025-10-23 | [RISCV] Rename RISCVISD::ABSW->NEGW_MAX. NFC (#164909) | Craig Topper |
| 2025-10-21 | [RISCV][LLVM] Enable atomics for 'Zalrsc' (#163672) | slachowsky |
| 2025-10-21 | [RISCV] Remove remapping Zfinx register classes to GPR class in getRegForInli... | Jim Lin |
| 2025-10-21 | [RISCV] Use CONCAT_VECTORS instead of INSERT_SUBVECTOR. NFC. (#164226) | Jim Lin |
| 2025-10-17 | [RISCV] Allow large div peephole optimization for minsize (#163679) | kvpanch |
| 2025-10-16 | [RISCV] Expand divisions larger than 64 bits on RV32. (#163688) | Craig Topper |
| 2025-10-08 | [RISCV] Use getNegative instead of subtracting from zero. NFC (#162313) | Sudharsan Veeravalli |
| 2025-10-07 | [RISCV][NFC] Avoid iteration and division while selecting SHXADD instructions... | Piotr Fusik |
| 2025-10-06 | [RISCV][GISel] Fallback to SelectionDAG for RVV tuple intrinsics. (#162133) | Craig Topper |
| 2025-10-06 | [RISCV] Add "MIPS" to name of MIPS-specific RISCVSubtarget functions. NFC (#1... | Craig Topper |
| 2025-10-03 | [RISCV] Support scalar llvm.fmodf intrinsic. (#161743) | Craig Topper |
| 2025-09-26 | Revert "[TTI][RISCV] Add cost modelling for intrinsic vp.load.ff (#160470)" | ShihPo Hung |
| 2025-09-26 | [TTI][RISCV] Add cost modelling for intrinsic vp.load.ff (#160470) | Shih-Po Hung |
| 2025-09-24 | [RISCV] Set riscv-fpimm-cost threshold to 3 by default (#159352) | Alex Bradbury |
| 2025-09-24 | [RISCV] Disable slideup optimization on the inconsistent element type of EVec... | Hongyu Chen |
| 2025-09-24 | [RISCV] Don't merge pseudo selects with stack adjustment instrs in between (#... | Elizaveta Noskova |
| 2025-09-24 | [RISCV] Refactor DAG-to-DAG Selection: Port lowering code for `qc.insb/qc.ins... | quic_hchandel |
| 2025-09-22 | [RISCV] Use isUInt<32> instead of <= 0xffffffff. NFC | Craig Topper |
| 2025-09-19 | [RISCV] Fix typo in comment. NFC | Craig Topper |
| 2025-09-19 | [RISCV] Use MutableArrayRef instead of SmallVectorImpl&. NFC (#159651) | Craig Topper |
| 2025-09-19 | [RISCV] Re-work how VWADD_W_VL and similar _W_VL nodes are handled in combine... | Craig Topper |
