| Age | Commit message (Expand) | Author |
|---|
| 2025-09-18 | [RISCV] Use Subtarget member variable instead of getting it from MachineFunct... | Craig Topper |
| 2025-09-19 | [RISCV] Move Xqci Select-likes to use riscv_selectcc (#153147) | Sam Elliott |
| 2025-09-18 | [RISCV] Pass SDValue by value. NFC | Craig Topper |
| 2025-09-18 | [RISCV] Match fmaxnum and fminnum to reduction ops. (#159244) | Jim Lin |
| 2025-09-18 | [RISCV][CodeGen] Add CodeGen support of Zibi experimental extension (#146858) | Boyao Wang |
| 2025-09-17 | [RISCV] Implement computeKnownBitsForTargetNode for SHL_ADD (#159105) | Piotr Fusik |
| 2025-09-17 | [RISCV] Lower (select c, (1 << X) + 1, 0) -> (shXadd c, c) (#158969) | Piotr Fusik |
| 2025-09-16 | [RISCV] Add hasREV8Like helper to RISCVSubtarget. NFC (#158775) | Craig Topper |
| 2025-09-16 | [RISCV] Improve fixed vector handling in isCtpopFast. (#158380) | Craig Topper |
| 2025-09-16 | [RISCV] Add helper method for shift-and-add extensions (#158638) | Piotr Fusik |
| 2025-09-15 | [RISCV] Check the types are the same for folding (sub 0, (setcc x, 0, setlt))... | Jim Lin |
| 2025-09-12 | [RISCV] Use hasCPOPLike in isCtpopFast and getPopcntSupport (#158371) | Craig Topper |
| 2025-09-12 | [RISC] Use hasBEXTILike in useInversedSetcc and shouldFoldSelectWithSingleBit... | Craig Topper |
| 2025-09-12 | [RISCV] Support umin/umax in tryFoldSelectIntoOp (#157548) | Philip Reames |
| 2025-09-12 | [RISCV] Enabled debug entry support by default (#157703) | Georgiy Samoylov |
| 2025-09-11 | [RISCV] Add helper functions to detect CLZ/CTZ/CPOP-like support. (#158148) | Craig Topper |
| 2025-09-11 | [RISCV] Use default promotion for i32 CTLZ on RV64 with XTHeadBb. (#157994) | Craig Topper |
| 2025-09-11 | [RISCV][GISel] Add initial support for rvv intrinsics (#156415) | Jianjian Guan |
| 2025-09-10 | [RISCV] Use default promotion for i32 CTLZ_ZERO_UNDEF on RV64 with XTHeadBb. ... | Craig Topper |
| 2025-09-10 | [RISCV] Add helper method for detecting BEXTI or TH_TST is supported. NFC (#1... | Craig Topper |
| 2025-09-10 | [RISCV] Extend zvqdot matching to handle disjoint or (#157901) | Hongyu Chen |
| 2025-09-10 | [RISCV] Add helper method for checking for Zicond or XVentanaCondOps. NFC (#1... | Craig Topper |
| 2025-09-10 | [RISCV] Fold (X & -(1 << C1) & 0xffffffff) == C2 << C1 to sraiw X, C1 == C2. ... | Craig Topper |
| 2025-09-10 | [RISCV][NFC] Fix a misnamed variable (#157686) | Piotr Fusik |
| 2025-09-09 | [RISCV] Add VendorXTHeadCondMov to useInversedSetcc. (#157758) | Craig Topper |
| 2025-09-09 | [RISCV] Undo fneg (fmul x, y) -> fmul x, (fneg y) transform (#157388) | Luke Lau |
| 2025-09-08 | [RISCV] Allow constants in tryFoldSelectIntoOp (#157376) | Philip Reames |
| 2025-09-05 | [RISCV] Check for legal type before calling getSimpleValueType() in matchSpla... | Craig Topper |
| 2025-09-06 | [RISCV] Use non-VP select in gather->strided load combine. NFCish (#157070) | Luke Lau |
| 2025-09-05 | [RISCV] Reorganize select lowering to pull binop expansion early (#156974) | Philip Reames |
| 2025-09-05 | [RISCV] Use QC_E_LI to materialise addresses (#155819) | Sudharsan Veeravalli |
| 2025-09-04 | [RISCV] Use arithmetic for select c, 0, simm12 even with zicond (#156957) | Philip Reames |
| 2025-09-03 | [RISCV] Fold (X & (7 << 29)) == 0 -> (srliw X, 29) == 0 for RV64. (#156769) | Craig Topper |
| 2025-09-03 | [RISCV] Fold (vslide1up undef, v, (extract_elt x, 0)) into (vslideup x, v, 1)... | Min-Yih Hsu |
| 2025-09-03 | [RISCV] add computeKnownBitsForTargetNode for RISCVISD::SRLW (#155995) | Shreeyash Pandey |
| 2025-09-03 | [RISCV] Add changes to have better coverage for qc.insb and qc.insbi (#154135) | quic_hchandel |
| 2025-09-03 | [RISCV] Fix incorrect folding of select on ctlz/cttz (#155231) | Mitch |
| 2025-09-02 | [RISCV] Use slideup to lower build_vector when all operand are (extract_eleme... | Min-Yih Hsu |
| 2025-08-30 | [RISCV] Add computeKnownBitsForTargetNode for RISCVISD::SRAW. (#156191) | Craig Topper |
| 2025-08-28 | [RISCV] Use XORI/SLLI/ADDI to when materializing select of constants (#155845) | Philip Reames |
| 2025-08-27 | [RISCV] Use SLLI/ADDI to when materializing select of constants (#155644) | Philip Reames |
| 2025-08-27 | [RISCV] Mark OR used in czero select lowering as disjoint (#155654) | Philip Reames |
| 2025-08-27 | [RISCV] Avoid recreating constants in LowerSelect [nfc] (#155628) | Philip Reames |
| 2025-08-27 | [RISCV] Add SRAW to ComputeNumSignBitsForTargetNode. (#155564) | Craig Topper |
| 2025-08-27 | [RISCV] Account for ADDI immediate range in select of two constants w/ zicond... | Philip Reames |
| 2025-08-27 | [RISCV] Added ROLW/RORW/SLLW/SRAW/SRLW for canCreateUndefOrPoisonForTargetNod... | Jasmine Tang |
| 2025-08-27 | [RISCV] Do not commute with shift if we might break a qc.shladd pattern (#155... | Sudharsan Veeravalli |
| 2025-08-26 | [RISCV] Lower (setugt X, 2047) as (setne (srl X, 11), 0) (#155541) | Craig Topper |
| 2025-08-25 | [RISCV] Add underscores to instructions names for Zimop/Zcmop. (#155289) | Craig Topper |
| 2025-08-22 | [RISCV] Mark More Fatal Errors as Usage/Internal (#154876) | Sam Elliott |
