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path: root/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
AgeCommit message (Expand)Author
2025-08-22[RISCV] Merge int_riscv_masked_atomicrmw_*_i32/i64 intrinsics using llvm_anyi...Craig Topper
2025-08-19[RISCV] Handle more cases when combining (vfmv.s.f (extract_subvector X, 0)) ...Min-Yih Hsu
2025-08-19[RISCV] Use OrigTy from InputArg/OutputArg (NFCI) (#154095)Nikita Popov
2025-08-18[RISCV] Fold (X & -4096) == 0 -> (X >> 12) == 0 (#154233)Craig Topper
2025-08-18[RISCV] Fold (sext_inreg (setcc), i1) -> (sub 0, (setcc). (#154206)Craig Topper
2025-08-18[llvm] Replace SmallSet with SmallPtrSet (NFC) (#154068)Kazu Hirata
2025-08-18[RISCV][llvm] Support fixed-length vector inline assembly constraints (#150724)Brandon Wu
2025-08-15[RISCV] Fold (sext_inreg (xor (setcc), -1), i1) -> (add (setcc), -1). (#153855)Craig Topper
2025-08-15[CodeGen] Give ArgListEntry a proper constructor (NFC) (#153817)Nikita Popov
2025-08-14[CodeGen] Remove unnecessary setTypeListBeforeSoften() parameter (NFC)Nikita Popov
2025-08-13[RISCV][RVV] Prohibit conversion of scalar store to single-element vse if vmv...Sergey Kachkov
2025-08-12[NFC][RISCV] Correct signed/unsigned in CommentSam Elliott
2025-08-12[RISCV] Fix Immediate Check for Xqcibi UGT (#153141)Sam Elliott
2025-08-08[RISCV] Add intrinsics for strided segment stores with fixed vectors (#152038)Min-Yih Hsu
2025-08-07[CodeGen] Move IsFixed into ArgFlags (NFCI) (#152319)Nikita Popov
2025-08-06[Target] Remove unnecessary casts (NFC) (#152262)Kazu Hirata
2025-08-05[VP][RISCV] Add a vp.load.ff intrinsic for fault only first load. (#128593)Craig Topper
2025-08-05[RISCV] Reuse lowerToScalableOp for more nodes. NFC (#151911)Luke Lau
2025-08-04[RISCV] canCreateUndefOrPoisonForTargetNode - RISCVISD::SELECT_CC is only for...Simon Pilgrim
2025-08-04[RISCV] Support resumable non-maskable interrupt handlers (#148134)Gergely Futo
2025-08-01[RISCV] Add intrinsics for strided segment loads with fixed vectors (#151611)Min-Yih Hsu
2025-07-30[llvm] Extract and propagate callee_type metadataPrabhu Rajasekaran
2025-07-30[RISCV] Support PreserveMost calling convention (#148214)Pengcheng Wang
2025-07-30Revert "[RISCV] Cost bf16/f16 vector non-unit memory accesses as legal withou...Luke Lau
2025-07-29[RISCV] Combine a vsse from a vsseg with one active segment (#151198)Philip Reames
2025-07-29[RISCV] Address post commit style suggestionPhilip Reames
2025-07-29[RISCV] Rewrite deinterleave load as vlse optimization as DAG combine (#150049)Philip Reames
2025-07-28[RISCV] Cost bf16/f16 vector non-unit memory accesses as legal without zvfhmi...Luke Lau
2025-07-25[RISCV] Implement load/store support for XAndesBFHCvt (#150350)Jim Lin
2025-07-24[RISCV] Guard against out of bound shifts in expandMul. (#150464)Craig Topper
2025-07-25[RISCV] Pass sign-extended value to isInt check in expandMul (#150211)Sudharsan Veeravalli
2025-07-22[RISCV] Add TUPLE_INSERT and TUPLE_EXTRACT to verifyTargetNode. (#150148)Craig Topper
2025-07-22[RISCV] Teach RISCVTargetLowering::isFPImmLegal about fli+fneg (#149075)Alex Bradbury
2025-07-16Remove unused variable (#149115)Serge Pavlov
2025-07-16[RISCV][FPE] Remove unused variable (#149054)Serge Pavlov
2025-07-16[RISCV][FPEnv] Lowering of fpmode intrinsics (#148569)Serge Pavlov
2025-07-16[RISCV] Implement Builtins for XAndesBFHCvt extension. (#148804)Jim Lin
2025-07-15[RISCV] Use masked segment LD/ST intrinsics in (de)interleaveN lowering [nfc]...Philip Reames
2025-07-14[llvm] Remove unused includes (NFC) (#148768)Kazu Hirata
2025-07-14[RISCV] Add ISel patterns for Xqciac QC_SHLADD instruction (#148256)Sudharsan Veeravalli
2025-07-11[RISCV] Add riscv_vlm/vsm to RISCVTargetLowering::getTgtMemIntrinsic. (#148265)Craig Topper
2025-07-11[RISCV][NFC] Split InterleavedAccess related TLI hooks into a separate file (...Min-Yih Hsu
2025-07-11[RISCV] Add ISel patterns for Xqciac QC.MULIADD instruction (#147661)Sudharsan Veeravalli
2025-07-11[RISCV] Add ISel patterns for Qualcomm uC Xqcics extension (#146675)quic_hchandel
2025-07-10[ISel/RISCV] Custom-lower vector [l]lround (#147713)Ramkumar Ramachandra
2025-07-10[TargetLowering] Change getOptimalMemOpType and findOptimalMemOpLowering to t...Boyao Wang
2025-07-09[IA] Partially revert interface change from 4a66baPhilip Reames
2025-07-09[IA] Support deinterleave intrinsics w/ fewer than N extracts (#147572)Philip Reames
2025-07-09[RISCV] Efficiently lower (select %cond, andn (f, x), f) using zicond (#147369)Ryan Buchner
2025-07-09[ISel/RISCV] Custom-promote [b]f16 in [l]lrint (#146507)Ramkumar Ramachandra
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