| Age | Commit message (Expand) | Author |
|---|
| 2025-11-22 | [RISCV] Support zilsd-4byte-align for i64 load/store in SelectionDAG. (#169182) | Craig Topper |
| 2025-11-21 | [RISCV] Incorporate scalar addends to extend vector multiply accumulate chain... | Ryan Buchner |
| 2025-11-21 | [RISCV] Update SpacemiT-X60 vector mask instructions latencies (#150644) | Mikhail R. Gadelha |
| 2025-11-21 | [llvm][RISCV] Implement Zilsd load/store pair optimization (#158640) | Brandon Wu |
| 2025-11-20 | [RISCV] Use SDT_RISCVIntUnaryOpW for RISCVISD::ABSW type profile. NFC (#168932) | Craig Topper |
| 2025-11-20 | [RISCV] Only add v2i32 to GPR regclass in the RV64 hardware mode. (#168930) | Craig Topper |
| 2025-11-20 | [RISCV][llvm] Select splat_vector(constant) with PLI (#168204) | Brandon Wu |
| 2025-11-20 | [RISCV] Only reduce VLs of instructions with demanded VLs (#168693) | Luke Lau |
| 2025-11-19 | [RISCV][DAGCombiner] Fix potential missed combine in VL->VW extension (#168026) | Kai Lin |
| 2025-11-19 | CodeGen: Add subtarget to TargetLoweringBase constructor (#168620) | Matt Arsenault |
| 2025-11-19 | [RISCV] Update X60 ReleaseAtCycles for Vector Integer Arithmetic Instructions... | Mikhail R. Gadelha |
| 2025-11-19 | [RISCV] Convert -mtune=generic to generic-rv32/rv64 in RISCVSubtarget::initia... | Craig Topper |
| 2025-11-19 | [RISCV][NewPM] Port RISCVCodeGenPrepare to the new pass manager (#168381) | Alex Bradbury |
| 2025-11-19 | [TTI] Use MemIntrinsicCostAttributes for getMaskedMemoryOpCost (#168029) | Shih-Po Hung |
| 2025-11-18 | [RISCV] Legalize misaligned unmasked vp.load/vp.store to vle8/vse8. (#167745) | Craig Topper |
| 2025-11-18 | [GISel][RISCV] Compute CTPOP of small odd-sized integer correctly (#168559) | Hongyu Chen |
| 2025-11-18 | [RISCV] Add an option to enable CFIInstrInserter. (#164477) | Mikhail Gudim |
| 2025-11-18 | [RISCV] Reduce minimum VL needed for vslidedown.vx in RISCVVLOptimizer (#168392) | Luke Lau |
| 2025-11-18 | [RISCV] Remove unused argument check (NFC) (#168313) | Garth Lei |
| 2025-11-17 | [RISCV] Remove Match_InvalidXSfmmVType. NFC (#168465) | Craig Topper |
| 2025-11-17 | [RISCV] Remove unused function declaration. NFC (#168459) | Craig Topper |
| 2025-11-17 | [RISCV] Fold Zba-expanded (mul (shr exact X, C1), C2) (#168019) | Piotr Fusik |
| 2025-11-17 | [llvm][RISCV] Support splat and vp_splat for zvfbfa codegen (#167920) | Brandon Wu |
| 2025-11-17 | [VP][RISCV] Enable promotion on fixed-length vp intrinsics with zvfbfmin (#16... | Brandon Wu |
| 2025-11-16 | [SelectionDAG] Verify SDTCisVT and SDTCVecEltisVT constraints (#150125) | Sergei Barannikov |
| 2025-11-14 | [llvm][RISCV] Support P extension CodeGen (#167882) | Brandon Wu |
| 2025-11-13 | [RISCV] For (2^N +/- 2^M) muls, prefer ADD to SUB (#166757) | Piotr Fusik |
| 2025-11-14 | [RISCV][llvm] Handle INSERT_VECTOR_ELT, EXTRACT_VECTOR_ELT codegen for zvfbfa... | Brandon Wu |
| 2025-11-13 | [RISCV] Fix RISCVInsertVSETVLI coalescing clobbering VL def segment (#167712) | Luke Lau |
| 2025-11-12 | [RISCV][GISel] Fallback to SelectionDAG for vleff intrinsics. (#167776) | Craig Topper |
| 2025-11-12 | [RISCV] Remove custom legalization of v2i16/v4i8 loads for P extension. (#167... | Craig Topper |
| 2025-11-12 | CodeGen: Remove target hook for terminal rule (#165962) | Matt Arsenault |
| 2025-11-12 | [RISCV] Expand multiplication by `2^N * 3/5/9 + 1` with SHL_ADD (#166933) | Piotr Fusik |
| 2025-11-12 | [RISCV] Update SpacemiT-X60 vector permutation instructions latencies (#152738) | Mikhail R. Gadelha |
| 2025-11-12 | [RISCV] Add short forward branch support for `lui`, `qc.li`, and `qc.e.li` (#... | quic_hchandel |
| 2025-11-11 | [RISCV] Remove implicit conversions of MCRegister to unsigned. NFC (#167588) | Craig Topper |
| 2025-11-11 | Remove unused <utility> inclusion | serge-sans-paille |
| 2025-11-11 | [RISCV][llvm] Preliminary P extension codegen support (#162668) | Brandon Wu |
| 2025-11-10 | RISCV: Enable terminal rule (#165961) | Matt Arsenault |
| 2025-11-10 | CodeGen: Remove TRI arguments from stack load/store hooks (#158240) | Matt Arsenault |
| 2025-11-10 | CodeGen: Remove TRI argument from getRegClass (#158225) | Matt Arsenault |
| 2025-11-10 | CodeGen: Keep reference to TargetRegisterInfo in TargetInstrInfo (#158224) | Matt Arsenault |
| 2025-11-10 | [RISCV][TTI] Fix crash of non-built-in vector type cost quering. (#167258) | Elvis Wang |
| 2025-11-10 | [RISCV][llvm] Support Smpmpmt version 0.6 (#166322) | Brandon Wu |
| 2025-11-10 | [llvm][RISCV] Support Zvfbfa codegen for fneg, fabs and copysign (#166944) | Brandon Wu |
| 2025-11-07 | [llvm][RISCV] Do not assume V extension on seeing vector type. (#166994) | Chenguang Wang |
| 2025-11-07 | [RISCV] Support outlining of CFI instructions in the machine outliner (#166149) | Sudharsan Veeravalli |
| 2025-11-06 | [RISCV] Optimize (and (icmp x, 0, neq), (icmp y, 0, neq)) utilizing zicond ex... | Ryan Buchner |
| 2025-11-07 | [RISCV] Use SLLI.UW in double-SHL_ADD multiplications (#166728) | Piotr Fusik |
| 2025-11-06 | [RISCV] More explicitly check that combineOp_VLToVWOp_VL removes the extends ... | Craig Topper |
