summaryrefslogtreecommitdiff
path: root/llvm/lib/Target
AgeCommit message (Expand)Author
2025-11-22[RISCV] Support zilsd-4byte-align for i64 load/store in SelectionDAG. (#169182)Craig Topper
2025-11-22[AMDGPU] Enable serializing of allocated preload kernarg SGPRs info (#168374)tyb0807
2025-11-21AMDGPU: Improve getShuffleCost accuracy for 8- and 16-bit shuffles (#168818)Nicolai Hähnle
2025-11-21AMDGPU: Handle invariant when lowering global loads (#168914)Matt Arsenault
2025-11-21[HLSL] Add Load overload with status (#166449)Joshua Batista
2025-11-21Revert "[AMDGPU] Remove leftover implicit operands from SI_SPILL/SI_RESTORE."...Nathan Corbyn
2025-11-21[RISCV] Incorporate scalar addends to extend vector multiply accumulate chain...Ryan Buchner
2025-11-21[ARM] Restore hasSideEffects flag on t2WhileLoopSetup (#168948)Sergei Barannikov
2025-11-21[AMDGPU] Handle AV classes in SIFixSGPRCopies::processPHINode (#169038)Jay Foad
2025-11-21AMDGPU: Stop implementing shouldCoalesce (#168988)Matt Arsenault
2025-11-21[AMDGPU] Enable multi-group xnack replay in hardware (GFX1250) (#169016)Christudasan Devadasan
2025-11-21[RISCV] Update SpacemiT-X60 vector mask instructions latencies (#150644)Mikhail R. Gadelha
2025-11-21[AArch64] Avoid introducing illegal types in LowerVECTOR_COMPRESS (NFC) (#168...Benjamin Maxwell
2025-11-21[NVPTX] Support for dense and sparse MMA intrinsics with block scaling. (#163...Kirill Vedernikov
2025-11-21[PowerPC] Replace vspltisw+vadduwm instructions with xxleqv+vsubuwm for addin...Himadhith
2025-11-21[NVPTX] Fix PTX and SM conditions for narrow FP conversions (#168680)Srinivasa Ravi
2025-11-21[PowerPC] Fix Wparentheses warningJim Lin
2025-11-21[llvm][RISCV] Implement Zilsd load/store pair optimization (#158640)Brandon Wu
2025-11-20AMDGPU: Don't duplicate implicit operands in 3-address conversion (#168426)Nicolai Hähnle
2025-11-20[RISCV] Use SDT_RISCVIntUnaryOpW for RISCVISD::ABSW type profile. NFC (#168932)Craig Topper
2025-11-20[RISCV] Only add v2i32 to GPR regclass in the RV64 hardware mode. (#168930)Craig Topper
2025-11-20AMDGPU: Handle invariant loads when considering if a load can be scalar (#168...Matt Arsenault
2025-11-20[X86] Lower mathlib call ldexp into scalef when avx512 is enabled (#166839)Kavin Gnanapandithan
2025-11-20AMDGPU: Fix treating divergent loads as uniform (#168785)Matt Arsenault
2025-11-20[LoongArch] TableGen-erate SDNode descriptions (#168129)Sergei Barannikov
2025-11-20[AArch64][PAC] Use enum to describe LR signing condition (NFC) (#168548)Anatoly Trosinenko
2025-11-20[HLSL] Implement the `fwidth` intrinsic for DXIL and SPIR-V target (#161378)Alexander Johnston
2025-11-20[LLVM][CodeGen][SVE] Only use unpredicated bfloat instructions when all lanes...Paul Walker
2025-11-20[AArch64][SVE] Implement demanded bits for @llvm.aarch64.sve.cntp (#168714)Benjamin Maxwell
2025-11-20Revert "[AMDGPU] Add wave reduce intrinsics for float types - 2 (#161… (#16...Aaditya
2025-11-20CodeGen: Add missing subtarget to TargetLoweringBase constructor for ARC, CSK...Jim Lin
2025-11-20[X86] EltsFromConsecutiveLoads - recognise reverse load patterns. (#168706)Simon Pilgrim
2025-11-20[WebAssembly] Lower ANY_EXTEND_VECTOR_INREG (#167529)Sam Parker
2025-11-20[AMDGPU] Add wave reduce intrinsics for float types - 2 (#161815)Aaditya
2025-11-20[AMDGPU] Add wave reduce intrinsics for float types - 1 (#161814)Aaditya
2025-11-20[RISCV][llvm] Select splat_vector(constant) with PLI (#168204)Brandon Wu
2025-11-20[RISCV] Only reduce VLs of instructions with demanded VLs (#168693)Luke Lau
2025-11-19[AMDGPU] Fixed crash in getLastMIForRegion when the region is empty. (#168653)Dhruva Chakrabarti
2025-11-19[AMDGPU] Prioritize allocation of low 256 VGPR classes (#167978)Stanislav Mekhanoshin
2025-11-20[SystemZ] Fix linux s390x main can't bootstrap itself on SanitizerSpecialCase...anoopkg6
2025-11-19[RISCV][DAGCombiner] Fix potential missed combine in VL->VW extension (#168026)Kai Lin
2025-11-19CodeGen: Add subtarget to TargetLoweringBase constructor (#168620)Matt Arsenault
2025-11-19[RISCV] Update X60 ReleaseAtCycles for Vector Integer Arithmetic Instructions...Mikhail R. Gadelha
2025-11-19[X86] X86ISelDAGToDAG - don't let ADD/SUB(X,1) -> SUB/ADD(X,-1) constant fold...Simon Pilgrim
2025-11-19[Hexagon] Enable soft bf16 in hexagon (#167924)Fateme Hosseini
2025-11-19[AArch64][GlobalISel] Added support for hadd family of intrinsics (#163985)Joshua Rodriguez
2025-11-19[llvm] Use llvm::size (NFC) (#168675)Kazu Hirata
2025-11-19[AMDGPU] Remove leftover implicit operands from SI_SPILL/SI_RESTORE. (#168546)LU-JOHN
2025-11-19[AArch64] Update zero latency instructions in Neoverse scheduling tables (#16...Simon Wallis
2025-11-19[AArch64] match TRN starting from undef elements (#167955)Philip Ginsbach-Chen
generated by cgit v1.2.3 (git 2.25.1) at 2026-05-31 21:06:39 +0000