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path: root/llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-idiv.ll
AgeCommit message (Expand)Author
2025-11-10RegisterCoalescer: Enable terminal rule by default for AMDGPU (#161621)Matt Arsenault
2025-11-07[AMDGPU] Delete redundant s_or_b32 (#165261)LU-JOHN
2025-10-22[AMDGPU] Reland "Remove redundant s_cmp_lg_* sX, 0" (#164201)LU-JOHN
2025-10-18Revert "[AMDGPU] Remove redundant s_cmp_lg_* sX, 0 " (#164116)Jan Patrick Lehr
2025-10-18[AMDGPU] Remove redundant s_cmp_lg_* sX, 0 (#162352)LU-JOHN
2025-10-17[AMDGPU] 32-bit ABS is a legal DAG node (#163907)LU-JOHN
2025-09-26[AMDGPU] Ensure divergence for v_alignbit (#129159)Jeffrey Byrnes
2025-09-25[AMDGPU] Calc IsVALU correctly during UADDO/USUBO selection (#159814)LU-JOHN
2025-09-06AMDGPU: Allow folding multiple uses of some immediates into copies (#154757)Matt Arsenault
2025-07-18[AMDGPU] Add freeze for LowerSELECT (#148796)Shoreshen
2025-05-29[AMDGPU] Handle CreateBinOp not returning BinaryOperator (#137791)anjenner
2025-04-10Reapply [AMDGPU] SIFixSgprCopies should not process twice VGPR to SGPR copies...alex-t
2025-04-10Revert "[AMDGPU] SIFixSgprCopies should not process twice VGPR to SGPR copies...Nico Weber
2025-04-10[AMDGPU] SIFixSgprCopies should not process twice VGPR to SGPR copies inserte...alex-t
2025-03-18AMDGPU: Move insertion into V2SCopies map (#130776)Matt Arsenault
2025-01-30PeepholeOpt: Do not add subregister indexes to reg_sequence operands (#124111)Matt Arsenault
2024-12-12 Reapply [AMDGPU] prevent shrinking udiv/urem if either operand exceeds signe...choikwa
2024-12-09Revert "Reapply "[AMDGPU] prevent shrinking udiv/urem if either operand is in...Joseph Huber
2024-12-06Reapply "[AMDGPU] prevent shrinking udiv/urem if either operand is in… (#11...choikwa
2024-11-20Revert "[AMDGPU] prevent shrinking udiv/urem if either operand is in (SignedM...Joseph Huber
2024-11-20[AMDGPU] prevent shrinking udiv/urem if either operand is in (SignedMax,Unsig...choikwa
2024-11-08Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#...Shilei Tian
2024-11-08Revert "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#1...Shilei Tian
2024-11-08[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)Shilei Tian
2024-11-06[LLVM][IR] Use splat syntax when printing Constant[Data]Vector. (#112548)Paul Walker
2024-08-12Reapply "[AMDGPU] Always lower s/udiv64 by constant to MUL" (#101942)Pierre van Houtryve
2024-08-02Revert "[AMDGPU] Always lower s/udiv64 by constant to MUL (#100723)"Fangrui Song
2024-08-02[AMDGPU] Always lower s/udiv64 by constant to MUL (#100723)Pierre van Houtryve
2024-07-23[AMDGPU] Codegen support for constrained multi-dword sloads (#96163)Christudasan Devadasan
2024-07-23[AMDGPU][SILoadStoreOptimizer] Merge constrained sloads (#96162)Christudasan Devadasan
2024-07-15Reapply "AMDGPU: Move attributor into optimization pipeline (#83131)" and fol...Matt Arsenault
2024-07-14Revert "AMDGPU: Move attributor into optimization pipeline (#83131)" and foll...dyung
2024-07-14AMDGPU: Move attributor into optimization pipeline (#83131)Matt Arsenault
2024-06-07[DAG] Always allow folding XOR patterns to ABS pre-legalization (#94601)Simon Pilgrim
2024-03-27[AMDGPU] Fix missing `IsExact` flag when expanding vector binary operator (#8...Shilei Tian
2023-10-31[AMDGPU] amdgpu-codegenprepare-idiv.ll - regenerate checks. NFC.Simon Pilgrim
2023-10-30[AMDGPU] Select 64-bit imm moves if can be encoded as 32 bit operand (#70395)Stanislav Mekhanoshin
2023-10-26[opt] Infer DataLayout from triple if not specifiedAlex Richardson
2023-10-19[AMDGPU] Constant fold FMAD_FTZ (#69443)Pierre van Houtryve
2023-10-09Revert "[CodeGen] Really renumber slot indexes before register allocation (#6...Jay Foad
2023-10-09[CodeGen] Really renumber slot indexes before register allocation (#67038)Jay Foad
2023-10-05[AMDGPU][CodeGen] Fold immediates in src1 operands of V_MAD/MAC/FMA/FMAC. (#6...Ivan Kosarev
2023-10-04Revert "[DAG] Attempt shl narrowing in SimplifyDemandedBits"Kirill Stoimenov
2023-10-04[DAG] Attempt shl narrowing in SimplifyDemandedBitsSimon Pilgrim
2023-09-19[CodeGen] Renumber slot indexes before register allocation (#66334)Jay Foad
2023-04-10[AMDGPU] Introduce SIInstrWorklist to process instructions in moveToVALUskc7
2023-03-12[DAG] visitAND - fold (and (any_ext V), c) -> (zero_ext (and (trunc V), c)) i...Simon Pilgrim
2022-12-19[AMDGPU] Convert some tests to opaque pointers (NFC)Nikita Popov
2022-11-16AMDGPU: Create poison values instead of undefMatt Arsenault
2022-09-15[AMDGPU] Always select s_cselect_b32 for uniform 'select' SDNodeAlexander Timofeev
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