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AgeCommit message (Expand)Author
2025-11-23Revert "[RegAlloc] Fix the terminal rule check for interfere with DstReg (#16...Aiden Grossman
2025-11-23[RegAlloc] Fix the terminal rule check for interfere with DstReg (#168661)hstk30-hw
2025-11-21AMDGPU: Add baseline test for split/widen invariant loads (#168913)Matt Arsenault
2025-11-21Revert "[AMDGPU] Remove leftover implicit operands from SI_SPILL/SI_RESTORE."...Nathan Corbyn
2025-11-21[AMDGPU] Handle AV classes in SIFixSGPRCopies::processPHINode (#169038)Jay Foad
2025-11-21AMDGPU: Stop implementing shouldCoalesce (#168988)Matt Arsenault
2025-11-21Fix test from #168609 (#169041)Walter Lee
2025-11-21[AMDGPU] Enable multi-group xnack replay in hardware (GFX1250) (#169016)Christudasan Devadasan
2025-11-20AMDGPU: Convert constant-address-space-32bit test to generated checks (#168975)Matt Arsenault
2025-11-20AMDGPU: Don't duplicate implicit operands in 3-address conversion (#168426)Nicolai Hähnle
2025-11-20[AMDGPU] Precommit test for issue in amdgpu-rewrite-agpr-copy-mfma, (#168609)hjagasiaAMD
2025-11-20AMDGPU: Handle invariant loads when considering if a load can be scalar (#168...Matt Arsenault
2025-11-20Reapply "DAG: Allow select ptr combine for non-0 address spaces" (#168292) (#...Matt Arsenault
2025-11-20[AMDGPU] Precommit tests for V_CVT_PK_[IU]16_F32 (#168893)Jay Foad
2025-11-20AMDGPU: Fix treating divergent loads as uniform (#168785)Matt Arsenault
2025-11-20Revert "[AMDGPU] Add wave reduce intrinsics for float types - 2 (#161… (#16...Aaditya
2025-11-20[AMDGPU] Add wave reduce intrinsics for float types - 2 (#161815)Aaditya
2025-11-20[AMDGPU] Add wave reduce intrinsics for float types - 1 (#161814)Aaditya
2025-11-19Re-land [Transform][LoadStoreVectorizer] allow redundant in Chain (#168135)Gang Chen
2025-11-20RenameIndependentSubregs: try to only implicit def used subregs (#167486)Carl Ritson
2025-11-19[AMDGPU] Fixed crash in getLastMIForRegion when the region is empty. (#168653)Dhruva Chakrabarti
2025-11-19[AMDGPU] Prioritize allocation of low 256 VGPR classes (#167978)Stanislav Mekhanoshin
2025-11-19[AMDGPU] Add baseline test to show spilling of wmma scale. NFC (#168163)Stanislav Mekhanoshin
2025-11-19[AMDGPU] Remove leftover implicit operands from SI_SPILL/SI_RESTORE. (#168546)LU-JOHN
2025-11-19[AMDGPU][SDAG] Only fold flat offsets if they are inbounds PTRADDs (#165427)Fabian Ritter
2025-11-19[AMDGPU] Ignore wavefront barrier latency during scheduling DAG mutation (#16...Carl Ritson
2025-11-18[AMDGPU][GlobalISel] Add regbankselect rules for G_FSHR (#159818)Anshil Gandhi
2025-11-19[AMDGPU] Adding instruction specific features (#167809)Shoreshen
2025-11-18[AMDGPU] Don't fold an i64 immediate value if it can't be replicated from its...Shilei Tian
2025-11-18[AMDGPU] Consider FLAT instructions for VMEM hazard detection (#137170)Robert Imschweiler
2025-11-18[AMDGPU][GlobalISel] Add RegBankLegalize support for G_IS_FPCLASS (#167575)vangthao95
2025-11-17[AMDGPU] update LDS block size for gfx1250 (#167614)Changpeng Fang
2025-11-17[AMDGPU][GlobalISel] Add RegBankLegalize support for G_FMUL (#167847)vangthao95
2025-11-17[AArch64][GlobalISel] Add combine for build_vector(unmerge, unmerge, undef, u...Ryan Cowan
2025-11-17[AMDGPU][NFC] Mark GEPs in flat offset folding tests as inbounds (#165426)Fabian Ritter
2025-11-17[DAG] Add strictfp implicit def reg after metadata. (#168282)David Green
2025-11-17[AMDGPU] Add amdgpu-lower-exec-sync pass to lower named-barrier globals (#165...Chaitanya
2025-11-17[AMDGPU] TableGen-erate SDNode descriptions (#168248)Sergei Barannikov
2025-11-16Revert "DAG: Allow select ptr combine for non-0 address spaces" (#168292)ronlieb
2025-11-15[AMDGPU] When shrinking and/or to bitset*, remove implicit scc def (#168128)LU-JOHN
2025-11-14AMDGPU: Select vector reg class for divergent build_vector (#168169)Matt Arsenault
2025-11-14AMDGPU: Consider isVGPRImm when forming constant from build_vector (#168168)Matt Arsenault
2025-11-15AMDGPU: Use vgpr to implement divergent i32->i64 anyext (#168167)Matt Arsenault
2025-11-14AMDGPU: Use v_mov_b32 to implement divergent zext i32->i64 (#168166)Matt Arsenault
2025-11-14[AMDGPU] Fix wrong MSB encoding for V_FMAMK instructions (#168107)Shilei Tian
2025-11-14Revert "[Transform][LoadStoreVectorizer] allow redundant in Chain (#1… (#16...Gang Chen
2025-11-14AMDGPU: Fix verifier error when waterfall call target is in AV register (#168...Matt Arsenault
2025-11-14AMDGPU: Constrain readfirstlane operand when writing to m0 (#168004)Matt Arsenault
2025-11-14AMDGPU: Constrain readfirstlane operand to vgpr_32 (#168001)Matt Arsenault
2025-11-14[AMDGPU] Ensure SCC is not live before shrinking to s_bitset* (#167907)LU-JOHN
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