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AgeCommit message (Expand)Author
2025-11-22[RISCV] Support zilsd-4byte-align for i64 load/store in SelectionDAG. (#169182)Craig Topper
2025-11-23Revert "[RegAlloc] Fix the terminal rule check for interfere with DstReg (#16...Aiden Grossman
2025-11-23[RegAlloc] Fix the terminal rule check for interfere with DstReg (#168661)hstk30-hw
2025-11-22[AMDGPU] Enable serializing of allocated preload kernarg SGPRs info (#168374)tyb0807
2025-11-22[DAGCombiner] Don't optimize insert_vector_elt into shuffle if implicit trunc...Hongyu Chen
2025-11-21AMDGPU: Add baseline test for split/widen invariant loads (#168913)Matt Arsenault
2025-11-21Revert "[AMDGPU] Remove leftover implicit operands from SI_SPILL/SI_RESTORE."...Nathan Corbyn
2025-11-21[RISCV] Incorporate scalar addends to extend vector multiply accumulate chain...Ryan Buchner
2025-11-21[ARM] Restore hasSideEffects flag on t2WhileLoopSetup (#168948)Sergei Barannikov
2025-11-21[AMDGPU] Handle AV classes in SIFixSGPRCopies::processPHINode (#169038)Jay Foad
2025-11-21AMDGPU: Stop implementing shouldCoalesce (#168988)Matt Arsenault
2025-11-21Fix test from #168609 (#169041)Walter Lee
2025-11-21[AMDGPU] Enable multi-group xnack replay in hardware (GFX1250) (#169016)Christudasan Devadasan
2025-11-21[NVPTX] Support for dense and sparse MMA intrinsics with block scaling. (#163...Kirill Vedernikov
2025-11-21[PowerPC] Replace vspltisw+vadduwm instructions with xxleqv+vsubuwm for addin...Himadhith
2025-11-21[llvm][RISCV] Implement Zilsd load/store pair optimization (#158640)Brandon Wu
2025-11-20AMDGPU: Convert constant-address-space-32bit test to generated checks (#168975)Matt Arsenault
2025-11-20AMDGPU: Don't duplicate implicit operands in 3-address conversion (#168426)Nicolai Hähnle
2025-11-20[AMDGPU] Precommit test for issue in amdgpu-rewrite-agpr-copy-mfma, (#168609)hjagasiaAMD
2025-11-20AMDGPU: Handle invariant loads when considering if a load can be scalar (#168...Matt Arsenault
2025-11-20Reapply "DAG: Allow select ptr combine for non-0 address spaces" (#168292) (#...Matt Arsenault
2025-11-20[AMDGPU] Precommit tests for V_CVT_PK_[IU]16_F32 (#168893)Jay Foad
2025-11-20[X86] Lower mathlib call ldexp into scalef when avx512 is enabled (#166839)Kavin Gnanapandithan
2025-11-20AMDGPU: Fix treating divergent loads as uniform (#168785)Matt Arsenault
2025-11-20[RISCV] Do not write .s file in a test (#168865)Mikhail Gudim
2025-11-20[HLSL] Implement the `fwidth` intrinsic for DXIL and SPIR-V target (#161378)Alexander Johnston
2025-11-20[LLVM][CodeGen][SVE] Only use unpredicated bfloat instructions when all lanes...Paul Walker
2025-11-20[AArch64][SVE] Implement demanded bits for @llvm.aarch64.sve.cntp (#168714)Benjamin Maxwell
2025-11-20Revert "[AMDGPU] Add wave reduce intrinsics for float types - 2 (#161… (#16...Aaditya
2025-11-20[X86] EltsFromConsecutiveLoads - recognise reverse load patterns. (#168706)Simon Pilgrim
2025-11-20[WebAssembly] Lower ANY_EXTEND_VECTOR_INREG (#167529)Sam Parker
2025-11-20[AMDGPU] Add wave reduce intrinsics for float types - 2 (#161815)Aaditya
2025-11-20[AMDGPU] Add wave reduce intrinsics for float types - 1 (#161814)Aaditya
2025-11-20[RISCV][llvm] Select splat_vector(constant) with PLI (#168204)Brandon Wu
2025-11-19[CFIInserter] Turn a reachable llvm_unreachable into a report_fatal_error. (#...Craig Topper
2025-11-20[RISCV] Only reduce VLs of instructions with demanded VLs (#168693)Luke Lau
2025-11-19Re-land [Transform][LoadStoreVectorizer] allow redundant in Chain (#168135)Gang Chen
2025-11-20RenameIndependentSubregs: try to only implicit def used subregs (#167486)Carl Ritson
2025-11-19[AMDGPU] Fixed crash in getLastMIForRegion when the region is empty. (#168653)Dhruva Chakrabarti
2025-11-19[AMDGPU] Prioritize allocation of low 256 VGPR classes (#167978)Stanislav Mekhanoshin
2025-11-19DAG: Use poison for some vector result widening (#168290)Matt Arsenault
2025-11-19[RISCV] Fix CFI Multiple Locations Test (#168772)Sam Elliott
2025-11-19[RISCV][DAGCombiner] Fix potential missed combine in VL->VW extension (#168026)Kai Lin
2025-11-19[AMDGPU] Add baseline test to show spilling of wmma scale. NFC (#168163)Stanislav Mekhanoshin
2025-11-19[X86] X86ISelDAGToDAG - don't let ADD/SUB(X,1) -> SUB/ADD(X,-1) constant fold...Simon Pilgrim
2025-11-19[Hexagon] Enable soft bf16 in hexagon (#167924)Fateme Hosseini
2025-11-19[AArch64][GlobalISel] Added support for hadd family of intrinsics (#163985)Joshua Rodriguez
2025-11-19[AMDGPU] Remove leftover implicit operands from SI_SPILL/SI_RESTORE. (#168546)LU-JOHN
2025-11-19[RISCV][test] Add sincos-expansion.ll test caseAlex Bradbury
2025-11-19[AArch64] match TRN starting from undef elements (#167955)Philip Ginsbach-Chen
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