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path: root/llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-idiv.ll
AgeCommit message (Expand)Author
2022-08-02[AMDGPU] avoid blind converting to VALU REG_SEQUENCE and PHIsAlexander Timofeev
2022-07-30[AMDGPU] Extend SILoadStoreOptimizer to s_load instructionsCarl Ritson
2022-07-29Revert "[AMDGPU] avoid blind converting to VALU REG_SEQUENCE and PHIs"Alexander Timofeev
2022-07-28[AMDGPU] avoid blind converting to VALU REG_SEQUENCE and PHIsAlexander Timofeev
2022-07-27[DAG] SimplifyDemandedBits - don't early-out for multiple use valuesSimon Pilgrim
2022-07-14[AMDGPU] Lowering VGPR to SGPR copies to v_readfirstlane_b32 if profitable.Alexander Timofeev
2022-05-18[AMDGPU] Aggressively fold immediates in SIShrinkInstructionsJay Foad
2022-05-18[AMDGPU] Aggressively fold immediates in SIFoldOperandsJay Foad
2022-05-14[DAG] Enable ISD::SHL SimplifyMultipleUseDemandedBits handling inside Simplif...Simon Pilgrim
2022-01-26[LSV] Vectorize loads of vectors by turning it into a larger vectorBenjamin Kramer
2022-01-11Revert D109159 : Revert "[amdgpu] Enable selection of `s_cselect_b64`."David Salinas
2022-01-05Revert "Revert D109159 "[amdgpu] Enable selection of `s_cselect_b64`.""Nico Weber
2022-01-05Revert D109159 "[amdgpu] Enable selection of `s_cselect_b64`."David Salinas
2021-12-01[AMDGPU] Set most sched model resource's BufferSize to oneAustin Kerbow
2021-11-19[AMDGPU] Use new opcode for indexed vgpr readsJay Foad
2021-11-12[AMDGPU] Simplify 64-bit division/remainder expansionJay Foad
2021-10-21[AMDGPU] Allow to use a whole register file on gfx90a for VGPRsStanislav Mekhanoshin
2021-10-13[AMDGPU] Enable load clustering in the post-RA schedulerJay Foad
2021-10-12Revert "[AMDGPU] Enable load clustering in the post-RA scheduler"Jay Foad
2021-10-12[AMDGPU] Enable load clustering in the post-RA schedulerJay Foad
2021-09-21[AMDGPU] Filtering out the inactive lanes bits when lowering copy to SCCalex-t
2021-09-14RegAllocGreedy: Account for reserved registers in num regs heuristicMatt Arsenault
2021-09-14[AMDGPU] Switch PostRA sched to MachineSchedJoe Nash
2021-09-07[amdgpu] Enable selection of `s_cselect_b64`.Michael Liao
2021-08-25[AMDGPU] Divergence-driven compare operations instruction selectionalex-t
2021-08-10AMDGPU: Add alloc priority to global rangesMatt Arsenault
2021-08-04[DAGCombiner][AMDGPU] Canonicalize constants to the RHS of MULHU/MULHS.Craig Topper
2021-06-30[AMDGPU] Add S_MOV_B64_IMM_PSEUDO for wide constantsStanislav Mekhanoshin
2021-06-18[AMDGPU] Update generated checks. NFC.Jay Foad
2021-05-14[AMDGPU] Update SCC defs to VCC when uses are changed to VCCBrendon Cahoon
2021-02-23[AMDGPU][SelectionDAG] Don't combine uniform multiplies to MUL_[UI]24Nicolai Hähnle
2021-02-19[AMDGPU] Add some GFX9 test coverage. NFC.Jay Foad
2020-09-14[AMDGPU] Don't cluster storesJay Foad
2020-08-09Fix 64-bit copy to SCCPiotr Sobczak
2020-07-17[MachineScheduler] Fix the TopDepth/BotHeightReduce latency heuristicsJay Foad
2020-07-08[AMDGPU] Fix and simplify AMDGPUTargetLowering::LowerUDIVREMJay Foad
2020-07-08[AMDGPU] Fix and simplify AMDGPUCodeGenPrepare::expandDivRem32Jay Foad
2020-06-25[AMDGPU] Select s_cselectPiotr Sobczak
2020-06-24Revert "[AMDGPU] Enable compare operations to be selected by divergence"Matt Arsenault
2020-06-24[AMDGPU] Enable compare operations to be selected by divergencealex-t
2020-06-19Revert "[AMDGPU] Select s_cselect"Piotr Sobczak
2020-06-19[AMDGPU] Select s_cselectPiotr Sobczak
2020-05-04[AMDGPU] Enable carry out ADD/SUB operations divergence driven instruction se...alex-t
2020-03-11[AMDGPU] Extend macro fusion for ADDC and SUBB to SUBBREVJay Foad
2020-02-19AMDGPU: Enable integer division bypassMatt Arsenault
2020-02-14AMDGPU: Add option to expand 64-bit integer division in IRMatt Arsenault
2020-02-11AMDGPU: Use conditions directly in division expansionMatt Arsenault
2020-02-11AMDGPU: Don't expand more special div cases in IRMatt Arsenault
2020-02-11AMDGPU: Add baseline tests for CGP div expansionMatt Arsenault
2020-02-11AMDGPU: Directly use rcp intrinsic in idiv expansionsMatt Arsenault
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