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path: root/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
AgeCommit message (Expand)Author
2025-11-12[RISCV] Add short forward branch support for `lui`, `qc.li`, and `qc.e.li` (#...quic_hchandel
2025-11-11[RISCV][llvm] Preliminary P extension codegen support (#162668)Brandon Wu
2025-11-10CodeGen: Remove TRI arguments from stack load/store hooks (#158240)Matt Arsenault
2025-11-10CodeGen: Keep reference to TargetRegisterInfo in TargetInstrInfo (#158224)Matt Arsenault
2025-11-07[RISCV] Support outlining of CFI instructions in the machine outliner (#166149)Sudharsan Veeravalli
2025-11-04[RISCV] Add short forward branch support for `mul` instruction (#166300)quic_hchandel
2025-10-31[RISCV] Mask integer and float loads as canFoldAsLoad for stackmaps (#165761)Philip Reames
2025-10-31[RISCV] Add short forward branch support for `min`, `max`, `maxu` and `minu` ...quic_hchandel
2025-10-21[RISCV] Remove unreachable break statements. NFC (#164481)Craig Topper
2025-10-18[RISCV] Support Zvfbfa codegen (#161158)Brandon Wu
2025-10-13[RISCV] Add XSfmm pseudo instruction and vset* insertion support (#143068)Brandon Wu
2025-10-07[RISCV][NFC] Avoid iteration and division while selecting SHXADD instructions...Piotr Fusik
2025-10-03[RISCV] Replace uses of RISCV::NoRegister with Register() or isValid. NFC (#1...Craig Topper
2025-10-01[RISCV] Add commutative support for Qualcomm uC Xqcics extension (#161328)quic_hchandel
2025-09-30[RISCV] Add commutative support for Qualcomm uC Xqcicm extension (#160653)quic_hchandel
2025-09-29[RISCV][NFC] Rename getOppositeBranchCondition (#160972)Sam Elliott
2025-09-23[CodeGen] Rename isReallyTriviallyReMaterializable [nfc]Philip Reames
2025-09-18[RISCV][CodeGen] Add CodeGen support of Zibi experimental extension (#146858)Boyao Wang
2025-09-16[RISCV] Add helper method for shift-and-add extensions (#158638)Piotr Fusik
2025-09-09[RISCV] Exclude LPAD in machine outliner (#157220)Jesse Huang
2025-09-08CodeGen: Pass SubtargetInfo to TargetGenInstrInfo constructors (#157337)Matt Arsenault
2025-09-05[RISCV] Use MRI from MachineFunction in isVLKnownLE. NFCLuke Lau
2025-09-05[RISCV] Handle non uimm5 VL constants in isVLKnownLE (#156639)Luke Lau
2025-08-21[RISCV] Optimize the spill/reload of segment registers (#153184)Pengcheng Wang
2025-08-04Revert "[X86][ARM][RISCV][XCore][M68K] Invert the low bit to get the inverse ...Craig Topper
2025-08-04[X86][ARM][RISCV][XCore][M68K] Invert the low bit to get the inverse predicat...AZero13
2025-07-25[RISCV] Remove now unused immzero operand type. NFCCraig Topper
2025-07-16[RISCV] Handle LHS == 0 in isVLKnownLE (#148860)Luke Lau
2025-07-14[RISCV] Replace tab character. NFCCraig Topper
2025-07-14[RISCV] Add ISel patterns for Xqciac QC_SHLADD instruction (#148256)Sudharsan Veeravalli
2025-07-03[RISCV] Added the MIPS prefetch extensions for MIPS RV64 P8700. (#145647)UmeshKalappa
2025-07-03[RISCV] Use template version isInt<N> instead. NFC.Jim Lin
2025-07-03[RISCV] Add isel patterns for generating XAndesPerf branch immediate instruct...Jim Lin
2025-07-01[RISCV] Factor out getKillRegState in copyPhysReg (NFC) (#146454)Sudharsan Veeravalli
2025-06-27[RISCV] Add nds.bfos and nds.bfoz for the short forward branch optimization. ...Jim Lin
2025-06-25[RISCV] Remove separate immediate condition codes from RISCVCC. NFC (#145762)Craig Topper
2025-06-25[RISCV] Explicitly check for supported opcodes in optimizeCondBranch. NFC (#1...Craig Topper
2025-06-25[RISCV] Remove -mattr=+no-rvc-hints (#145138)Craig Topper
2025-06-24[RISCV] Fix a correctness issue in optimizeCondBranch. Prevent optimizing com...Craig Topper
2025-06-23[RISCV][NFC] Remove hasStdExtCOrZca (#145139)Sam Elliott
2025-06-13[RISCV] Simplify macros used for commuting vector multiply-accumulate instruc...Craig Topper
2025-06-13[RISCV] Simplify macros used by RISCVInstrInfo::convertToThreeAddress. NFC (#...Craig Topper
2025-06-13[RISCV] Use RISCVII::getVecPolicyOpNum instead of making assumptions. NFC (#...Craig Topper
2025-06-13[RISCV] Use unsigned instead of uint16_t for the Opcode argument to getVector...Craig Topper
2025-06-12[RISCV] Remove implicit $vl def on vleNff pseudos (#143935)Luke Lau
2025-06-06[RISCV] Add missing immediate operand type for verifyInstruction. NFC. (#143056)Jim Lin
2025-05-30[RISCV] Use isVLPreservingConfig in isConvertibleToVMV_V_V. NFCCraig Topper
2025-05-29[RISCV] Canonicalize beq/bne with x0 as first arg to beqz/bnez (#141781)Alex Bradbury
2025-05-29[RISCV] Add bltu/bgeu zero => bnez/beqz canonicalisation to RISCVInstrInfo::s...Alex Bradbury
2025-05-28[RISCV] Use isVectorConfigInstr in isConvertibleToVMV_V_V. NFC (#141874)Craig Topper
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