| Age | Commit message (Expand) | Author |
|---|
| 2025-11-09 | [Target] Fix misleading indentation (NFC) (#167206) | Kazu Hirata |
| 2025-10-04 | [ARM] Auto-decode vpred_n/vpred_r operands (#160282) | Sergei Barannikov |
| 2025-09-23 | [NFC][MC][ARM] Reorder decoder functions N/N (#158767) | Rahul Joshi |
| 2025-09-23 | [ARM] Auto-decode s_cc_out operand (#159956) | Sergei Barannikov |
| 2025-09-19 | [ARM] Verify that disassembled instruction is correct (#157360) | Sergei Barannikov |
| 2025-09-08 | [NFC][MC][ARM] Reorder decoder functions 5/N (#156920) | Rahul Joshi |
| 2025-09-04 | [NFC][MC][ARM] Reorder decoder functions 4/N (#156690) | Rahul Joshi |
| 2025-09-03 | [NFC][MC][ARM] Rearrange decoder functions 3/N (#156240) | Rahul Joshi |
| 2025-08-31 | [NFC][ARM][MC] Rearrange decoder functions 2/N (#155464) | Rahul Joshi |
| 2025-08-26 | [NFC][MC][ARM] Rearrange decode functions in ARM disassembler (#154988) | Rahul Joshi |
| 2025-08-21 | [NFC][MC][Decoder] Extract fixed pieces of decoder code into new header file ... | Rahul Joshi |
| 2025-08-21 | [NFC][MC][ARM] Fix formatting for `ITStatus` and `VPTStatus` (#154815) | Rahul Joshi |
| 2025-08-21 | [ARM][Disassembler] Advance IT State when instruction is unknown (#154531) | Peter Smith |
| 2025-07-13 | [ARM] Remove unnecessary casts (NFC) (#148533) | Kazu Hirata |
| 2025-06-17 | [llvm] annotate interfaces in llvm/Target for DLL export (#143615) | Andrew Rogers |
| 2025-03-19 | [ARM] Use MCPhysReg instead of uint16_t for arrays of registers. NFC | Craig Topper |
| 2024-11-07 | [ARM] Allow spilling FPSCR for MVE adc/sbc intrinsics (#115174) | Oliver Stannard |
| 2024-10-18 | [ARM] Use ARM::NoRegister in more places. NFC | David Green |
| 2024-10-17 | Fix MSVC signed/unsigned mismatch warning. NFC. | Simon Pilgrim |
| 2024-10-17 | [ARM] Fix problems with register list in vscclrm (#111825) | John Brawn |
| 2024-10-16 | [ARM] Fix warnings in ARMAsmParser.cpp and ARMDisassembler.cpp (#112507) | Karl-Johan Karlsson |
| 2024-09-21 | [ARM] Use MCRegister in more places. NFC | Craig Topper |
| 2024-03-11 | [llvm][arm] add T1 and T2 assembly options for vlldm and vlstm | Sivan Shani |
| 2024-02-29 | Revert "[llvm][arm] add T1 and T2 assembly options for vlldm and vlstm (#83116)" | Tomas Matheson |
| 2024-02-28 | [llvm][arm] add T1 and T2 assembly options for vlldm and vlstm (#83116) | SivanShani-Arm |
| 2023-10-10 | Use llvm::endianness::{big,little,native} (NFC) | Kazu Hirata |
| 2023-10-09 | Use llvm::endianness{,::little,::native} (NFC) | Kazu Hirata |
| 2023-09-01 | [llvm] Fix duplicate word typos. NFC | Fangrui Song |
| 2023-06-26 | Move SubtargetFeature.h from MC to TargetParser | Job Noorman |
| 2023-02-17 | Simplify with hasFeature. NFC | Fangrui Song |
| 2023-02-13 | [ARM] Use llvm::rotl and llvm::rotr (NFC) | Kazu Hirata |
| 2023-01-28 | [Target] Use llvm::count{l,r}_{zero,one} (NFC) | Kazu Hirata |
| 2023-01-23 | [MC] Make more use of MCInstrDesc::operands. NFC. | Jay Foad |
| 2023-01-12 | [ARM] Use MCInstrInfo::get in ARMDisassembler instead of reinventing it | Jay Foad |
| 2022-12-07 | [TableGen] More named sub-operands work. | James Y Knight |
| 2022-10-28 | [llvm-tblgen] NFC: Simplify DecoderEmitter. | James Y Knight |
| 2022-08-08 | [llvm] LLVM_FALLTHROUGH => [[fallthrough]]. NFC | Fangrui Song |
| 2022-08-08 | [llvm-objdump,ARM] Fix big-endian AArch32 disassembly. | Simon Tatham |
| 2022-07-26 | [MC,llvm-objdump,ARM] Target-dependent disassembly resync policy. | Simon Tatham |
| 2022-05-25 | [MCDisassembler] Disambiguate Size parameter in tryAddingSymbolicOperand() | Maksim Panchenko |
| 2022-05-15 | Rename `MCFixedLenDisassembler.h` as `MCDecoderOps.h` | Sheng |
| 2022-03-25 | [Disassember][NFCI] Use strong type for instruction decoder | Maksim Panchenko |
| 2022-03-17 | [ARM] Fix Decode of tsb csync | Archibald Elliott |
| 2021-11-30 | [clang][ARM] PACBTI-M assembly support | Ties Stuij |
| 2021-10-08 | Move TargetRegistry.(h|cpp) from Support to MC | Reid Kleckner |
| 2021-09-02 | [ARM] Add a tail-predication loop predicate register | David Green |
| 2021-08-16 | [ARM] Create MQQPR and MQQQQPR register classes | David Green |
| 2021-04-25 | [ARM][disassembler] Fix incorrect number of MCOperands generated by the disas... | Min-Yih Hsu |
| 2020-11-18 | ADT: Add assertions to SmallVector::insert, etc., for reference invalidation | Duncan P. N. Exon Smith |
| 2020-07-22 | [ARM] Fix Asm/Disasm of TBB/TBH instructions | David Spickett |
