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path: root/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
AgeCommit message (Expand)Author
2020-04-07[ARM] Remove condition that could never be truePeter Smith
2020-02-17[ARM] Add initial support for Custom Datapath Extension (CDE)Mikhail Maltsev
2020-01-23[ARM,MVE] Revise immediate VBIC/VORR to look more like NEON.Simon Tatham
2020-01-14CMake: Make most target symbols hidden by defaultTom Stellard
2020-01-14[ARM][Thumb2] Fix ADD/SUB invalid writes to SPDiogo Sampaio
2020-01-11[Disassembler] Delete the VStream parameter of MCDisassembler::getInstruction()Fangrui Song
2020-01-10Reverting, broke some bots. Need further investigation.Diogo Sampaio
2020-01-10[ARM][Thumb2] Fix ADD/SUB invalid writes to SPDiogo Sampaio
2019-09-09[ARM][MVE] Decoding of uqrshl and sqrshl accepts unpredictable encodingsOliver Stannard
2019-07-28[ARM] MVE VPNOTDavid Green
2019-07-23[ARM] Rename NEONModImm to VMOVModImm. NFCDavid Green
2019-07-19[ARM] Add <saturate> operand to SQRSHRL and UQRSHLLMikhail Maltsev
2019-06-28[ARM] Fix integer UB in MVE load/store immediate handling.Simon Tatham
2019-06-27[ARM] Fix handling of zero offsets in LOB instructions.Simon Tatham
2019-06-27[ARM] Make coprocessor number restrictions consistent.Simon Tatham
2019-06-27[ARM] Tighten restrictions on use of SP in v8.1-M CSEL.Simon Tatham
2019-06-25[ARM] Add remaining miscellaneous MVE instructions.Simon Tatham
2019-06-25[ARM] Add MVE vector load/store instructions.Simon Tatham
2019-06-24[ARM] Add MVE interleaving load/store family.Simon Tatham
2019-06-21Fix MSVC "result of 32-bit shift implicitly converted to 64 bits" warning. NFCI.Simon Pilgrim
2019-06-21[ARM] Add MVE 64-bit GPR <-> vector move instructions.Simon Tatham
2019-06-21[ARM] Add MVE vector instructions that take a scalar input.Simon Tatham
2019-06-21[ARM] Add a batch of similarly encoded MVE instructions.Simon Tatham
2019-06-21[ARM] Fix -Wimplicit-fallthrough after D62675Fangrui Song
2019-06-21[ARM] Add MVE vector compare instructions.Simon Tatham
2019-06-21[ARM] Add a batch of MVE floating-point instructions.Simon Tatham
2019-06-20[ARM] Add a batch of MVE integer instructions.Simon Tatham
2019-06-20[llvm-objdump] Switch between ARM/Thumb based on mapping symbols.Eli Friedman
2019-06-19[ARM] Add MVE vector bit-operations (register inputs).Simon Tatham
2019-06-18[ARM] Rename MVE instructions in Tablegen for consistency.Simon Tatham
2019-06-13[ARM] Set up infrastructure for MVE vector instructions.Simon Tatham
2019-06-13[ARM] Refactor handling of IT mask operands.Simon Tatham
2019-06-11[ARM] First MVE instructions: scalar shifts.Mikhail Maltsev
2019-06-11[ARM] Add the non-MVE instructions in Arm v8.1-M.Simon Tatham
2019-06-11Revert CMake: Make most target symbols hidden by defaultTom Stellard
2019-06-10CMake: Make most target symbols hidden by defaultTom Stellard
2019-06-10Revert rL362953 and its followup rL362955.Simon Tatham
2019-06-10[ARM] Add the non-MVE instructions in Arm v8.1-M.Simon Tatham
2019-05-28[ARM] Replace fp-only-sp and d16 with fp64 and d32.Simon Tatham
2019-05-14[ARM] Create a TargetInfo header. NFCRichard Trieu
2019-04-23ARM: disallow add/sub to sp unless Rn is also sp.Tim Northover
2019-03-08[ARM][FIX] Fix vfmal.f16 and vfmsl.f16 operandDiogo N. Sampaio
2019-02-25[ARM] Make fullfp16 instructions not conditionalisable.Simon Tatham
2019-01-19Update the file headers across all of the LLVM projects in the monorepoChandler Carruth
2018-07-30Remove trailing spaceFangrui Song
2018-06-26ARM: correctly decode VFP instructions following unpredictable t2ITTim Northover
2018-06-26ARM: diagnose unpredictable IT instructionsTim Northover
2018-03-06[ARM]Decoding MSR with unpredictable destination register causes an assertSimi Pallipurath
2018-02-08[ARM] Re-commit r324600 with fixed LLVMBuild.txtOliver Stannard
2018-02-08Revert r324600 as it breaks a buildbotOliver Stannard
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