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path: root/llvm/lib/Target/AMDGPU/VOP3PInstructions.td
AgeCommit message (Expand)Author
2025-11-12[AMDGPU] Change encoding of gfx1250 ld_scale (#167777)Stanislav Mekhanoshin
2025-11-04[AMDGPU] Mark WMMA machine instructions as convergent (#165602)Syadus Sefat
2025-10-23[AMDGPU] Change patterns for v_[pk_]add_{min|max} (#164881)Stanislav Mekhanoshin
2025-10-22[AMDGPU] Add intrinsics for v_[pk]_add_{min|max}_* instructions (#164731)Stanislav Mekhanoshin
2025-10-10AMDGPU/GlobalISel: Fix using wrong regbank for smfmac (#162762)Matt Arsenault
2025-10-08AMDGPU: Use RegClassByHwMode to manage operand VGPR operand constraints (#158...Matt Arsenault
2025-10-07AMDGPU: Track minNumAGPRs in MFI instead of mayUseAGPRs (#161996)Matt Arsenault
2025-09-30[AMDGPU] Introduce and use NotUseRealTrue16Insts. NFC. (#161373)Jay Foad
2025-09-24[AMDGPU][True16][CodeGen] true16 isel pattern for fma_mix_f16/bf16 (#159648)Brox Chen
2025-09-11[AMDGPU] Restrict to VGPR only for mfma scale operands (#158117)Changpeng Fang
2025-09-10[AMDGPU] Restrict operands of ld_scale_paired to low 256 vgprs. NFCI (#157935)Stanislav Mekhanoshin
2025-09-09[AMDGPU] Combine VGPRSrc and VGPROp definitions into VGPROp (#157516)Joe Nash
2025-09-08[AMDGPU] Restrict scale operands of WMMA to low 256 VGPRs (#157526)Stanislav Mekhanoshin
2025-08-30[TableGen][CodeGen] Remove DisableEncoding field of Instruction class (#156098)Sergei Barannikov
2025-08-05[AMDGPU] Add gfx1250 wmma_scale[16]_f32_32x16x128_f4 instructions (#152194)Stanislav Mekhanoshin
2025-08-04[AMDGPU] Add fixed size to wmma instructions with scale (#152043)Stanislav Mekhanoshin
2025-08-04[AMDGPU] gfx1250 v_wmma_scale[16]_f32_16x16x128_f8f6f4 codegen (#152036)Stanislav Mekhanoshin
2025-08-04[AMDGPU] Add gfx1250 v_wmma_scale[16]_f32_16x16x128_f8f6f4 MC support (#152014)Stanislav Mekhanoshin
2025-08-04[AMDGPU] Use SDNodeXForm to select a few VOP3P modifiers, NFC (#151907)Changpeng Fang
2025-08-04[AMDGPU] gfx1250 v_wmma_ld_scale instructions (#152010)Stanislav Mekhanoshin
2025-07-25[AMDGPU] Support AMDGPUClamp for bf16 on gfx1250 (#150663)Changpeng Fang
2025-07-24[AMDGPU] Add v_fma_mix_f32_f16 as an alias of v_fma_mix_f32 on gfx1250 (#150502)Changpeng Fang
2025-07-24[AMDGPU] Support V_FMA_MIX*_BF16 instructions on gfx1250 (#150381)Changpeng Fang
2025-07-23[AMDGPU] Support V_PK_MIN3/MAX3_NUM_F16 on gfx1250 (#150326)Changpeng Fang
2025-07-23AMDGPU: Support V_PK_MAXIMUM3_F16 and V_PK_MINIMUM3_F16 on gfx1250 (#150307)Changpeng Fang
2025-07-23AMDGPU: Support packed bf16 instructions on gfx1250 (#150283)Changpeng Fang
2025-07-23AMDGPU: Add packed fp32 instructions for gfx1250 (#150253)Changpeng Fang
2025-07-23AMDGPU: Support V_PK_ADD_{MIN|MAX}_{I|U}16 and V_{MIN|MAX}3_{I|U}16 on gfx125...Changpeng Fang
2025-07-21AMDGPU: Support v_wmma_f32_16x16x128_f8f6f4 on gfx1250 (#149684)Changpeng Fang
2025-07-15AMDGPU: Support intrinsic selection for gfx1250 wmma instructions (#148957)Changpeng Fang
2025-07-15AMDGPU: Implement MC layer support for gfx1250 wmma instructions. (#148570)Changpeng Fang
2025-07-08[AMDGPU] Add FeatureIEEEMinimumMaximumInsts. NFCI. (#147594)Stanislav Mekhanoshin
2025-06-05[AMDGPU][MC] Allow dpp in v_dot2_f32_bf16 for GFX11 and 12 (#142451)Jun Wang
2025-05-21[AMDGPU] Fix scale opsel flags for scaled MFMA operations (#140183)Vigneshwar Jayakumar
2025-04-21[AMDGPU] Correct VOP3P encoding. NFC. (#136005)Stanislav Mekhanoshin
2025-03-01AMDGPU: Sort an instruction definition by opcode (#129350)Matt Arsenault
2025-02-21AMDGPU: Form v2f16 minimum3/maximum3 on gfx950 (#128123)Matt Arsenault
2025-02-19[AMDGPU] Add `isAsCheapAsAMove` for `v_pk_mov_b32` (#127632)Shilei Tian
2025-02-13[AMDGPU] Simplify OtherPredicates handling in MadFmaMixPats. NFC. (#127044)Jay Foad
2025-02-11[AMDGPU][True16][CodeGen] true16 codegen for MadFmaMixPat (#124892)Brox Chen
2024-12-18[AMDGPU][MC] Disallow op_sel in some VOP3P dot instructions (#100485)Jun Wang
2024-12-13AMDGPU: Fix entry for mac in VGPR->AGPR MFMA table (#119693)Matt Arsenault
2024-12-09[AMDGPU] New GFX11+ aliases v_dot4_i32_i8 and v_dot8_i32_i4 (#118997)Jay Foad
2024-12-02AMDGPU: Create InstrMapping from VGPR MFMA to equivalent AGPR instruction (#1...Matt Arsenault
2024-11-26AMDGPU: Make v2f16 minimum/maximum legal for gfx950 (#117738)Matt Arsenault
2024-11-25AMDGPU: Add minimum3/maximum3 pkf16 for gfx950 encodings (#117601)Matt Arsenault
2024-11-25AMDGPU: Add support for v_dot2_f32_bf16 instruction for gfx950 (#117597)Matt Arsenault
2024-11-22AMDGPU: Add v_smfmac_f32_32x32x64_fp8_fp8 for gfx950 (#117259)Matt Arsenault
2024-11-22AMDGPU: Add v_smfmac_f32_32x32x32x64_fp8_bf8 for gfx950 (#117258)Matt Arsenault
2024-11-22AMDGPU: Add v_smfmac_f32_32x32x64_bf8_fp8 for gfx950 (#117257)Matt Arsenault
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