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path: root/llvm/lib/Target/AMDGPU
AgeCommit message (Expand)Author
2025-11-22[AMDGPU] Enable serializing of allocated preload kernarg SGPRs info (#168374)tyb0807
2025-11-21AMDGPU: Improve getShuffleCost accuracy for 8- and 16-bit shuffles (#168818)Nicolai Hähnle
2025-11-21AMDGPU: Handle invariant when lowering global loads (#168914)Matt Arsenault
2025-11-21Revert "[AMDGPU] Remove leftover implicit operands from SI_SPILL/SI_RESTORE."...Nathan Corbyn
2025-11-21[AMDGPU] Handle AV classes in SIFixSGPRCopies::processPHINode (#169038)Jay Foad
2025-11-21AMDGPU: Stop implementing shouldCoalesce (#168988)Matt Arsenault
2025-11-21[AMDGPU] Enable multi-group xnack replay in hardware (GFX1250) (#169016)Christudasan Devadasan
2025-11-20AMDGPU: Don't duplicate implicit operands in 3-address conversion (#168426)Nicolai Hähnle
2025-11-20AMDGPU: Handle invariant loads when considering if a load can be scalar (#168...Matt Arsenault
2025-11-20AMDGPU: Fix treating divergent loads as uniform (#168785)Matt Arsenault
2025-11-20Revert "[AMDGPU] Add wave reduce intrinsics for float types - 2 (#161… (#16...Aaditya
2025-11-20[AMDGPU] Add wave reduce intrinsics for float types - 2 (#161815)Aaditya
2025-11-20[AMDGPU] Add wave reduce intrinsics for float types - 1 (#161814)Aaditya
2025-11-19[AMDGPU] Fixed crash in getLastMIForRegion when the region is empty. (#168653)Dhruva Chakrabarti
2025-11-19[AMDGPU] Prioritize allocation of low 256 VGPR classes (#167978)Stanislav Mekhanoshin
2025-11-19CodeGen: Add subtarget to TargetLoweringBase constructor (#168620)Matt Arsenault
2025-11-19[llvm] Use llvm::size (NFC) (#168675)Kazu Hirata
2025-11-19[AMDGPU] Remove leftover implicit operands from SI_SPILL/SI_RESTORE. (#168546)LU-JOHN
2025-11-19[AMDGPU][SDAG] Only fold flat offsets if they are inbounds PTRADDs (#165427)Fabian Ritter
2025-11-19[AMDGPU] Ignore wavefront barrier latency during scheduling DAG mutation (#16...Carl Ritson
2025-11-18[AMDGPU][GlobalISel] Add regbankselect rules for G_FSHR (#159818)Anshil Gandhi
2025-11-19[AMDGPU] Adding instruction specific features (#167809)Shoreshen
2025-11-18[NFC] Check operand type instead of opcode (#168641)Shilei Tian
2025-11-18[AMDGPU] Don't fold an i64 immediate value if it can't be replicated from its...Shilei Tian
2025-11-18[NFC][AMDGPU] IGLP: Fixes for unsigned int handling (#135090)Robert Imschweiler
2025-11-18[AMDGPU] Consider FLAT instructions for VMEM hazard detection (#137170)Robert Imschweiler
2025-11-18[AMDGPU][GlobalISel] Add RegBankLegalize support for G_IS_FPCLASS (#167575)vangthao95
2025-11-18[AMDGPU] Remove const on a return type. (#168490)Kazu Hirata
2025-11-18[AMDGPU][SIMemoryLegalizer] Combine GFX10-11 CacheControl Classes (#168058)Pierre van Houtryve
2025-11-17[AMDGPU] update LDS block size for gfx1250 (#167614)Changpeng Fang
2025-11-17[AMDGPU] Fix layering violations in AMDGPUMCExpr.cpp. NFC (#168242)Craig Topper
2025-11-17[AMDGPU][GlobalISel] Add RegBankLegalize support for G_FMUL (#167847)vangthao95
2025-11-17[AMDGPU][SIMemoryLegalizer] Combine all GFX6-9 CacheControl Classes (#168052)Pierre van Houtryve
2025-11-17[AMDGPU] Add amdgpu-lower-exec-sync pass to lower named-barrier globals (#165...Chaitanya
2025-11-17[AMDGPU] TableGen-erate SDNode descriptions (#168248)Sergei Barannikov
2025-11-15[AMDGPU] When shrinking and/or to bitset*, remove implicit scc def (#168128)LU-JOHN
2025-11-14AMDGPU: Select vector reg class for divergent build_vector (#168169)Matt Arsenault
2025-11-14AMDGPU: Consider isVGPRImm when forming constant from build_vector (#168168)Matt Arsenault
2025-11-15AMDGPU: Use vgpr to implement divergent i32->i64 anyext (#168167)Matt Arsenault
2025-11-14AMDGPU: Use v_mov_b32 to implement divergent zext i32->i64 (#168166)Matt Arsenault
2025-11-15[AMDGPU] Delete some dead code (NFC) (#167891)Sergei Barannikov
2025-11-14[AMDGPU] Fix wrong MSB encoding for V_FMAMK instructions (#168107)Shilei Tian
2025-11-14[AMDGPU][MC] Disallow nogds in ds_gws_* instructions (#166873)Jun Wang
2025-11-14[AMDGPU] Use std::variant in ArgDescriptor. (#167992)Craig Topper
2025-11-14AMDGPU: Fix verifier error when waterfall call target is in AV register (#168...Matt Arsenault
2025-11-14AMDGPU: Constrain readfirstlane operand when writing to m0 (#168004)Matt Arsenault
2025-11-14AMDGPU: Constrain readfirstlane operand to vgpr_32 (#168001)Matt Arsenault
2025-11-14[TableGen] Split *GenRegisterInfo.inc. (#167700)Ivan Kosarev
2025-11-14[AMDGPU] Ensure SCC is not live before shrinking to s_bitset* (#167907)LU-JOHN
2025-11-14[AMDGPU][True16][CodeGen] lower flat_d16_saddr_t16 to saddr inst (#166603)Brox Chen
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