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path: root/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
AgeCommit message (Expand)Author
2025-11-21AMDGPU: Stop implementing shouldCoalesce (#168988)Matt Arsenault
2025-11-14[AMDGPU] Make use of getFunction and getMF. NFC. (#167872)Jay Foad
2025-11-14AMDGPU: Remove getProperlyAlignedRC (#167993)Matt Arsenault
2025-11-13AMDGPU: Really use AV classes by default for vector classes (#166483)Matt Arsenault
2025-11-13[AMDGPU] Use MCRegUnit, insert explicit casts to/from unsigned (NFC) (#167889)Sergei Barannikov
2025-11-13AMDGPU: Start to use AV classes for unknown vector class (#166482)Matt Arsenault
2025-11-12[CodeGen] Use MCRegUnit in two more TRI methods (NFC) (#167680)Sergei Barannikov
2025-11-11AMDGPU: Remove wrapper around TRI::getRegClass (#159885)Matt Arsenault
2025-11-11AMDGPU: Start using RegClassByHwMode for wavesize operandsMatt Arsenault
2025-11-11AMDGPU: Relax shouldCoalesce to allow more register tuple widening (#166475)Matt Arsenault
2025-11-11AMDGPU: Replace some uses of getOpRegClass with getRegClass (#167447)Matt Arsenault
2025-10-29[AMDGPU] Support true16 spill restore with sram-ecc (#165320)Stanislav Mekhanoshin
2025-10-27[AMDGPU] Use implicit operand to preserve liveness of COPY (#164911)Jeffrey Byrnes
2025-10-12[llvm] Use [[fallthrough]] instead of LLVM_FALLTHROUGH (NFC) (#163086)Kazu Hirata
2025-10-08AMDGPU: Use RegClassByHwMode to manage operand VGPR operand constraints (#158...Matt Arsenault
2025-10-07AMDGPU: Stop using the wavemask register class for SCC cross class copies (#1...Matt Arsenault
2025-10-06AMDGPU: Stop handling AGPR case in getCrossCopyRegClass (#161800)Matt Arsenault
2025-10-03AMDGPU: Fix trying to constrain physical registers in spill handling (#161793)Matt Arsenault
2025-09-12CodeGen: Remove MachineFunction argument from getPointerRegClass (#158185)Matt Arsenault
2025-09-05AMDGPU: Use switch to implement getRegPressureSetLimit (#156993)Matt Arsenault
2025-09-03[AMDGPU] Define 1024 VGPRs on gfx1250 (#156765)Stanislav Mekhanoshin
2025-09-02AMDGPU: Add VS_64_Align2 class (#156132)Matt Arsenault
2025-08-05[AMDGPU] Add MC support for new gfx1250 src_flat_scratch_base_lo/hi (#152203)Stanislav Mekhanoshin
2025-07-28AMDGPU: Move getMaxNumVectorRegs into GCNSubtarget (NFC) (#150889)Matt Arsenault
2025-07-21[AMDGPU] ISel & PEI for whole wave functions (#145858)Diana Picus
2025-07-18[AMDGPU] Use SIRegisterInfo to compute used registers. NFCI (#149051)Diana Picus
2025-07-09[AMDGPU][True16][CodeGen] stop emitting spgr_lo16 from isel (#144819)Brox Chen
2025-07-03AMDGPU: Implement tensor load and store instructions for gfx1250 (#146636)Changpeng Fang
2025-07-01AMDGPU: Implement ds_atomic_async_barrier_arrive_b64/ds_atomic_barrier_arrive...Changpeng Fang
2025-06-24[AMDGPU] Replace dynamic VGPR feature with attribute (#133444)Diana Picus
2025-06-13Revert "[AMDGPU] Skip register uses in AMDGPUResourceUsageAnalysis (#… (#14...Diana Picus
2025-06-04[AMDGPU] Use MachineRegisterInfo::def_instructions (NFC) (#142782)Kazu Hirata
2025-06-03[AMDGPU] Skip register uses in AMDGPUResourceUsageAnalysis (#133242)Diana Picus
2025-05-05[AMDGPU] Remove implicit definition of register group when restoring the last...Ryan Buchner
2025-04-25Reland [AMDGPU] Support block load/store for CSR #130013 (#137169)Diana Picus
2025-04-23Revert "[AMDGPU] Support block load/store for CSR" (#136846)Diana Picus
2025-04-23[AMDGPU] Support block load/store for CSR (#130013)Diana Picus
2025-03-19[AMDGPU] Allocate scratch space for dVGPRs for CWSR (#130055)Diana Picus
2025-03-17[AMDGPU] frame index elimination hit assertion for scavenged nonreg (#130287)Pankaj Dwivedi
2025-03-12[AMDGPU][True16] added Pre-RA hint to improve copy elimination (#103366)Brox Chen
2025-03-06AMDGPU: Replace amdgpu-no-agpr with amdgpu-agpr-alloc (#129893)Matt Arsenault
2025-03-06AMDGPU: Add amdgpu-agpr-alloc attribute to control AGPR allocation (#128034)Matt Arsenault
2025-03-05AMDGPU: Handle s_add_u32 in eliminateFrameIndex (#129628)Matt Arsenault
2025-03-03[AMDGPU] Simplify conditional expressions. NFC. (#129228)Jay Foad
2025-02-26[AMDGPU][True16][CodeGen] 16bit spill support in true16 mode (#128060)Brox Chen
2025-02-26[AMDGPU] Do not allow M0 as v_readlane_b32 dst (#128867)Pierre van Houtryve
2025-02-26[AMDGPU] Do not allow M0 as v_readfirstlane_b32 dst (#128851)Pierre van Houtryve
2025-02-25[AMDGPU][True16][CodeGen] uaddsat/usubsat true16 selection in gisel (#128233)Brox Chen
2025-02-23AMDGPU: Respect amdgpu-no-agpr in functions and with calls (#128147)Matt Arsenault
2025-02-07AMDGPU: Use default shouldRewriteCopySrc (#125535)Matt Arsenault
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