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path: root/llvm/lib/Target/AMDGPU/SILowerI1Copies.cpp
AgeCommit message (Expand)Author
2025-11-11AMDGPU: Start using RegClassByHwMode for wavesize operandsMatt Arsenault
2025-05-23[NFC][CodeGen] Adopt MachineFunctionProperties convenience accessors (#141101)Rahul Joshi
2025-03-27[AMDGPU] Use MapVector instead of DenseMap (NFC) (#133356)Kazu Hirata
2024-12-13Reapply "[DomTreeUpdater] Move critical edge splitting code to updater" (#119...paperchalice
2024-12-11Revert "[DomTreeUpdater] Move critical edge splitting code to updater" (#119512)paperchalice
2024-12-11[DomTreeUpdater] Move critical edge splitting code to updater (#115111)paperchalice
2024-11-13[AMDGPU] Remove unused includes (NFC) (#116154)Kazu Hirata
2024-08-10AMDGPU/NewPM: Port SILowerI1Copies to new pass manager (#102663)Matt Arsenault
2024-07-11Revert "[CodeGen] Remove `applySplitCriticalEdges` in `MachineDominatorTree` ...Nikita Popov
2024-07-11[CodeGen] Remove `applySplitCriticalEdges` in `MachineDominatorTree` (#97055)paperchalice
2024-06-12[CodeGen][NewPM] Split `MachinePostDominators` into a concrete analysis resul...paperchalice
2024-06-11[CodeGen][NewPM] Split `MachineDominatorTree` into a concrete analysis result...paperchalice
2024-02-05AMDGPU/GlobalISelDivergenceLowering: select divergent i1 phis (#80003)Petar Avramovic
2024-01-24Revert "AMDGPU/GlobalISelDivergenceLowering: select divergent i1 phis" (#79274)Petar Avramovic
2024-01-24AMDGPU/GlobalISelDivergenceLowering: select divergent i1 phis (#78482)Petar Avramovic
2024-01-17Revert "AMDGPU/GlobalISelDivergenceLowering: select divergent i1 phis" (#78468)Petar Avramovic
2024-01-17AMDGPU/GlobalISelDivergenceLowering: select divergent i1 phis (#76145)Petar Avramovic
2023-12-15AMDGPU: refactor phi lowering from SILowerI1Copies (NFCI) (#75349)Petar Avramovic
2023-11-15AMDGPU/SILowerI1Copies process phi incomings in specific order (#72375)petar-avramovic
2023-11-15AMDGPU/SILowerI1Copies: refactor phi incoming handling [NFC] (#72374)petar-avramovic
2023-09-11[AMDGPU] SILowerI1Copies: clear kill flags on COPY (#65883)Carl Ritson
2022-09-14AMDGPU: Factor out hasDivergentBranch(). NFCRuiling Song
2022-02-17[AMDGPU] Return better Changed status from SILowerI1CopiesJay Foad
2021-07-27AMDGPU: Treat IMPLICIT_DEF like a constant lanemask sourceMatt Arsenault
2021-01-24[Target] Use llvm::append_range (NFC)Kazu Hirata
2021-01-23Revert "[Target] Use llvm::append_range (NFC)"Kazu Hirata
2021-01-23[Target] Use llvm::append_range (NFC)Kazu Hirata
2021-01-20[NFC][AMDGPU] Split AMDGPUSubtarget.h to R600 and GCN subtargetsdfukalov
2021-01-07[NFC][AMDGPU] Reduce include files dependency.dfukalov
2020-12-04[AMDGPU] Use llvm::is_contained (NFC)Kazu Hirata
2020-08-21[AMDGPU] Apply llvm-prefer-register-over-unsigned from clang-tidyJay Foad
2020-08-20[AMDGPU] Remove uses of Register::isPhysicalRegister/isVirtualRegisterJay Foad
2020-02-17AMDGPU/GlobalISel: Skip DAG hack passes on selected functionsMatt Arsenault
2019-11-13Sink all InitializePasses.h includesReid Kleckner
2019-10-26[AMDGPU] Fix Vreg_1 PHI lowering in SILowerI1Copies.cdevadas
2019-09-25[Dominators][AMDGPU] Don't use virtual exit node in findNearestCommonDominato...Jakub Kuderski
2019-09-09AMDGPU: Make VReg_1 size be 1Matt Arsenault
2019-08-15Apply llvm-prefer-register-over-unsigned from clang-tidy to LLVMDaniel Sanders
2019-08-01Finish moving TargetRegisterInfo::isVirtualRegister() and friends to llvm::Re...Daniel Sanders
2019-06-27AMDGPU: Make fixing i1 copies robust against re-orderingNicolai Haehnle
2019-06-16[AMDGPU] gfx10 conditional registers handlingStanislav Mekhanoshin
2019-04-23AMDGPU: Fix LCSSA phi lowering in SILowerI1CopiesNicolai Haehnle
2019-03-18[AMDGPU] Asm/disasm v_cndmask_b32_e64 with abs/neg source modifiersTim Renouf
2019-01-19Update the file headers across all of the LLVM projects in the monorepoChandler Carruth
2018-10-31AMDGPU: Rewrite SILowerI1Copies to always stay on SALUNicolai Haehnle
2018-07-11AMDGPU: Refactor Subtarget classesTom Stellard
2018-05-22AMDGPU: Remove #include "MCTargetDesc/AMDGPUMCTargetDesc.h" from common headersTom Stellard
2018-04-04AMDGPU: Fix copying i1 value out of loop with non-uniform exitNicolai Haehnle
2017-12-13Rename LiveIntervalAnalysis.h to LiveIntervals.hMatthias Braun
2017-09-29AMDGPU: VALU carry-in and v_cndmask condition cannot be EXECNicolai Haehnle
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