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path: root/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
AgeCommit message (Expand)Author
2025-11-21Revert "[AMDGPU] Remove leftover implicit operands from SI_SPILL/SI_RESTORE."...Nathan Corbyn
2025-11-20AMDGPU: Don't duplicate implicit operands in 3-address conversion (#168426)Nicolai Hähnle
2025-11-19[AMDGPU] Remove leftover implicit operands from SI_SPILL/SI_RESTORE. (#168546)LU-JOHN
2025-11-15[AMDGPU] When shrinking and/or to bitset*, remove implicit scc def (#168128)LU-JOHN
2025-11-14AMDGPU: Fix verifier error when waterfall call target is in AV register (#168...Matt Arsenault
2025-11-14[AMDGPU] Make use of getFunction and getMF. NFC. (#167872)Jay Foad
2025-11-13[AMDGPU] Lower S_ABSDIFF_I32 to VALU instructions (#167691)Mariusz Sikora
2025-11-12CodeGen/AMDGPU: Allow 3-address conversion of bundled instructions (#166213)Nicolai Hähnle
2025-11-11AMDGPU: Remove override of TargetInstrInfo::getRegClass (#159886)Matt Arsenault
2025-11-11AMDGPU: Remove wrapper around TRI::getRegClass (#159885)Matt Arsenault
2025-11-11[AMDGPU] Generate s_lshl?_add_u32 (#167032)LU-JOHN
2025-11-10CodeGen: Remove TRI arguments from stack load/store hooks (#158240)Matt Arsenault
2025-11-10CodeGen: Remove TRI argument from reMaterialize (#158229)Matt Arsenault
2025-11-10CodeGen: Remove TRI argument from getRegClass (#158225)Matt Arsenault
2025-11-10CodeGen: Keep reference to TargetRegisterInfo in TargetInstrInfo (#158224)Matt Arsenault
2025-11-07[AMDGPU] Delete redundant s_or_b32 (#165261)LU-JOHN
2025-11-06Reland: CodeGen: Record MMOs in finalizeBundle (#166689)Nicolai Hähnle
2025-11-04[AMDGPU][NFC] Avoid copying MachineOperands (#166293)LU-JOHN
2025-11-02[llvm] Remove "const" in the presence of "constexpr" (NFC) (#166109)Kazu Hirata
2025-10-31[AMDGPU][NFC] Refactor SCC optimization (#165871)LU-JOHN
2025-10-22[AMDGPU] Reland "Remove redundant s_cmp_lg_* sX, 0" (#164201)LU-JOHN
2025-10-20AMDGPU: Refactor three-address conversion (NFC) (#162558)Nicolai Hähnle
2025-10-18Revert "[AMDGPU] Remove redundant s_cmp_lg_* sX, 0 " (#164116)Jan Patrick Lehr
2025-10-18[AMDGPU] Remove redundant s_cmp_lg_* sX, 0 (#162352)LU-JOHN
2025-10-17[AMDGPU][True16][CodeGen] S_PACK_XX_B32_B16 lowering for true16 mode (#162389)Brox Chen
2025-10-14[AMDGPU] Simplify vcc handling in copyPhysReg. NFC. (#163340)Jay Foad
2025-10-13[AMDGPU] Enable saving SHARED_BASE to VCC (#163244)carlobertolli
2025-10-08AMDGPU: Use RegClassByHwMode to manage operand VGPR operand constraints (#158...Matt Arsenault
2025-10-03[AMDGPU][True16][CodeGen] fix v_mov_b16_t16 index in folding pass (#161764)Brox Chen
2025-10-03AMDGPU: Stop trying to constrain register class of post-RA-pseudos (#161792)Matt Arsenault
2025-10-03AMDGPU: Remove dead code trying to constrain a physical register (#161790)Matt Arsenault
2025-10-01[AMDGPU][InsertWaitCnts] Refactor some helper functions, NFC (#161160)Pierre van Houtryve
2025-09-24[AMDGPU][True16][CodeGen] true16 isel pattern for fma_mix_f16/bf16 (#159648)Brox Chen
2025-09-23[CodeGen] Rename isReallyTriviallyReMaterializable [nfc]Philip Reames
2025-09-22[AMDGPU] Skip debug uses in SIInstrInfo::foldImmediate (#160102)Jay Foad
2025-09-19[AMDGPU]: Unpack packed instructions overlapped by MFMAs post-RA scheduling (...Akash Dutta
2025-09-19AMDGPU: Remove unnecessary AGPR legalize logic (#159491)Matt Arsenault
2025-09-18AMDGPU: Remove unnecessary operand legalization for WMMAs (#159370)Matt Arsenault
2025-09-18AMDGPU: Constrain regclass when replacing SGPRs with VGPRs (#159369)Matt Arsenault
2025-09-16[AMDGPU] Use larger immediate values in S_NOP (#158990)Jay Foad
2025-09-16[AMDGPU] Drop high 32 bits of aperture registers (#158725)Stanislav Mekhanoshin
2025-09-16[AMDGPU] Refactor out common exec mask opcode patterns (NFCI) (#154718)Carl Ritson
2025-09-13AMDGPU: Relax verifier for agpr/vgpr loads and stores (#158391)Matt Arsenault
2025-09-12CodeGen: Remove MachineFunction argument from getRegClass (#158188)Matt Arsenault
2025-09-12AMDGPU: Move spill pseudo special case out of adjustAllocatableRegClass (#158...Matt Arsenault
2025-09-12AMDGPU: Remove MIMG special case in adjustAllocatableRegClass (#158184)Matt Arsenault
2025-09-12AMDGPU: Relax legal register operand constraint (#157989)Matt Arsenault
2025-09-12AMDGPU: Stop checking allocatable in adjustAllocatableRegClass (#158105)Matt Arsenault
2025-09-10AMDGPU/UniformityAnalysis: fix G_ZEXTLOAD and G_SEXTLOAD (#157845)Petar Avramovic
2025-09-08[AMDGPU] Restrict scale operands of WMMA to low 256 VGPRs (#157526)Stanislav Mekhanoshin
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