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path: root/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
AgeCommit message (Expand)Author
2025-11-21AMDGPU: Handle invariant when lowering global loads (#168914)Matt Arsenault
2025-11-20Revert "[AMDGPU] Add wave reduce intrinsics for float types - 2 (#161… (#16...Aaditya
2025-11-20[AMDGPU] Add wave reduce intrinsics for float types - 2 (#161815)Aaditya
2025-11-20[AMDGPU] Add wave reduce intrinsics for float types - 1 (#161814)Aaditya
2025-11-19CodeGen: Add subtarget to TargetLoweringBase constructor (#168620)Matt Arsenault
2025-11-17[AMDGPU] TableGen-erate SDNode descriptions (#168248)Sergei Barannikov
2025-11-14[AMDGPU] Make use of getFunction and getMF. NFC. (#167872)Jay Foad
2025-11-13AMDGPU: Really use AV classes by default for vector classes (#166483)Matt Arsenault
2025-11-13AMDGPU: Start to use AV classes for unknown vector class (#166482)Matt Arsenault
2025-11-11AMDGPU: Replace some uses of getOpRegClass with getRegClass (#167447)Matt Arsenault
2025-10-30[AMDGPU] Support bfloat comparison for ballot intrinsic (#165495)Changpeng Fang
2025-10-29[AMDGPU] Support image atomic no return instructions (#150742)Harrison Hao
2025-10-23[AMDGPU][NFC] Cleanly make 32-bit abs legal (#164837)LU-JOHN
2025-10-20[AMDGPU] Enable volatile and non-temporal for loads to LDS (#153244)Krzysztof Drewniak
2025-10-14[llvm] Replace LLVM_ATTRIBUTE_UNUSED with [[maybe_unused]] (NFC) (#163330)Kazu Hirata
2025-10-10AMDGPU: Stop using aligned VGPR classes for addRegisterClass (#158278)Matt Arsenault
2025-10-08[AMDGPU] Remove setcc by using add/sub carryout (#155255)LU-JOHN
2025-10-07AMDGPU: Remove unnecessary AGPR operand legalization (#162093)Matt Arsenault
2025-10-07AMDGPU: Track minNumAGPRs in MFI instead of mayUseAGPRs (#161996)Matt Arsenault
2025-10-03DAG: Remove TargetLowering::checkForPhysRegDependency (#161787)Matt Arsenault
2025-10-04CodeGen: Do not store RegisterClass copy costs as a signed value (#161786)Matt Arsenault
2025-10-02[AMDGPU][SDAG] Enable ISD::PTRADD for 64-bit AS by default (#146076)Fabian Ritter
2025-09-25[AMDGPU] Calc IsVALU correctly during UADDO/USUBO selection (#159814)LU-JOHN
2025-09-25[AMDGPU] Fix vector legalization for bf16 valu ops (#158439)Giuseppe Rossini
2025-09-24[AMDGPU] Add the support for 45-bit buffer resource (#159702)Shilei Tian
2025-09-24[NFC][AMDGPU] Refactor common declarations (#160406)LU-JOHN
2025-09-23[AMDGPU] Support `xor cond, -1` when lowering `BRCOND` (#160341)Shilei Tian
2025-09-23Revert "[AMDGPU] Elide bitcast fold i64 imm to build_vector" (#160325)Janek van Oirschot
2025-09-22[NFC][AMDGPU] Streamline code (#160177)LU-JOHN
2025-09-22[AMDGPU] Use unsigned overflow for S_UADDO_PSEUDO/S_USUBO_PSEUDO (#160142)LU-JOHN
2025-09-19[SDAG][AMDGPU] Allow opting in to OOB-generating PTRADD transforms (#146074)Fabian Ritter
2025-09-19[AMDGPU][SDAG] Handle ISD::PTRADD in various special cases (#145330)Fabian Ritter
2025-09-16[AMDGPU] Set TGID_EN_X/Y/Z when cluster ID intrinsics are used (#159120)Shilei Tian
2025-09-16[AMDGPU] Elide bitcast fold i64 imm to build_vector (#154115)Janek van Oirschot
2025-09-16[AMDGPU] Fix codegen to emit COPY instead of S_MOV_B64 for aperture regs (#15...Stanislav Mekhanoshin
2025-09-16[AMDGPU] Refactor out common exec mask opcode patterns (NFCI) (#154718)Carl Ritson
2025-09-15AMDGPU: Report unaligned scratch access as fast if supported by tgt (#158036)macurtis-amd
2025-09-12[AMDGPU] Support lowering of cluster related instrinsics (#157978)Shilei Tian
2025-09-12[AMDGPU] Remove an unused variable (NFC)Jie Fu
2025-09-12AMDGPU: Fix returning wrong type for stack passed sub-dword arguments (#158002)Matt Arsenault
2025-09-11[AMDGPU][SDAG] Legalise v2i32 or/xor/and instructions to make use of 64-bit w...Chris Jackson
2025-09-11[AMDGPU] Use subtarget call to determine number of VGPRs (#157927)Stanislav Mekhanoshin
2025-09-10[AMDGPU] Extending wave reduction intrinsics for `i64` types - 3 (#151310)Aaditya
2025-09-10[AMDGPU] Extending wave reduction intrinsics for `i64` types - 2 (#151309)Aaditya
2025-09-10[AMDGPU] Extending wave reduction intrinsics for `i64` types - 1 (#150169)Aaditya
2025-09-08[AMDGPU] Constrain inline asm vgprs to low 256 (#157531)Stanislav Mekhanoshin
2025-09-04[AMDGPU][gfx1250] Add 128B cooperative atomics (#156418)Pierre van Houtryve
2025-09-04[AMDGPU] Tail call support for whole wave functions (#145860)Diana Picus
2025-09-03[AMDGPU] Define 1024 VGPRs on gfx1250 (#156765)Stanislav Mekhanoshin
2025-09-03[AMDGPU] Support cluster_load_async_to_lds instructions on gfx1250 (#156595)Changpeng Fang
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