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path: root/llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp
AgeCommit message (Expand)Author
2025-11-18[AMDGPU] Consider FLAT instructions for VMEM hazard detection (#137170)Robert Imschweiler
2025-11-13[AMDGPU] Use MCRegUnit, insert explicit casts to/from unsigned (NFC) (#167889)Sergei Barannikov
2025-11-04[llvm] Use conventional enum declarations (NFC) (#166318)Kazu Hirata
2025-10-28[AMDGPU] Rework GFX11 VALU Mask Write Hazard (#138663)Carl Ritson
2025-10-08AMDGPU: Use RegClassByHwMode to manage operand VGPR operand constraints (#158...Matt Arsenault
2025-09-24[AMDGPU] Refine GCNHazardRecognizer hasHazard() (#138841)Carl Ritson
2025-09-23[AMDGPU] Handle S_GETREG_B32_const in the hazard recognizer. NFCI (#160364)Stanislav Mekhanoshin
2025-08-18[AMDGPU] Make use of SIInstrInfo::isWaitcnt. NFC. (#154087)Jay Foad
2025-08-15[AMDGPU] Use encodeFieldVaVdst in hazard recognizer. NFCI. (#153881)Stanislav Mekhanoshin
2025-08-15[AMDGPU] Update GCNHazardRecognizer's understanding of gfx12 waitcount instru...Stanislav Mekhanoshin
2025-08-15[AMDGPU] w/a for s_setreg_b32 gfx1250 hazard with MODE register (#153879)Stanislav Mekhanoshin
2025-08-15[AMDGPU] w/a hazard with writing s102/103 and reading FLAT_SCRATCH_BASE (#153...Stanislav Mekhanoshin
2025-08-15[AMDGPU] Mitigate DS_ATOMIC_ASYNC_BARRIER_ARRIVE_B64 bug (#153872)Stanislav Mekhanoshin
2025-08-15[AMDGPU] Handle S_GETREG_B32 hazard on gfx1250 (#153848)Stanislav Mekhanoshin
2025-08-01[AMDGPU] gfx1250 v_permlane_* instructions (#151749)Stanislav Mekhanoshin
2025-07-21[AMDGPU] Hazard handling for gfx1250 wmma instructions (#149865)Changpeng Fang
2025-07-21[AMDGPU] ISel & PEI for whole wave functions (#145858)Diana Picus
2025-07-16AMDGPU: Handle the co-execution hazards for TRANS for gfx1250 (#149024)Changpeng Fang
2025-07-02[AMDGPU] Add a debug option `-amdgpu-snop-padding` for `GCNHazardRecognizer` ...Shilei Tian
2025-06-05[AMDGPU] Support bottom-up postRA scheduing. (#135295)Harrison Hao
2025-05-07[AMDGPU] Classify FLAT instructions as VMEM (#137148)Robert Imschweiler
2025-03-14[AMDGPU][True16][CodeGen] add v_cndmask_t16 to hazardmask (#128912)Brox Chen
2025-02-28[AMDGPU][NFC] Move isXDL and isDGEMM to SIInstrInfo. (#129103)sstipano
2025-02-19[AMDGPU] Replace gfx940 and gfx941 with gfx942 in llvm (#126763)Fabian Ritter
2025-02-12[TableGen] Emit OpName as an enum class instead of a namespace (#125313)Rahul Joshi
2025-02-12AMDGPU: Handle gfx950 XDL Write-VGPR-VALU-WAW wait state change (#126132)Vigneshwar Jayakumar
2025-02-12AMDGPU: Handle gfx950 XDL-write-VGPR-VALU-Mem-Exp wait state change (#126727)Vigneshwar Jayakumar
2025-02-11AMDGPU: Handle gfx950 XDL-write-VGPR-Overlap-Src-AB wait state (#126732)Vigneshwar Jayakumar
2025-01-30[AMDGPU] Rewrite GFX12 SGPR hazard handling to dedicated pass (#118750)Carl Ritson
2025-01-21[AMDGPU] Fix crash due to missing check for FLAT instructions that dont use v...Chinmay Deshpande
2025-01-16[AMDGPU][True16][MC][CodeGen] true16 for v_cndmask_b16 (#119736)Brox Chen
2024-12-11[AMDGPU] Handle hazard in v_scalef32_sr_fp4_* conversions (#118589)Pravin Jagtap
2024-12-02AMDGPU: Handle cvt_scale F32/F16->F4/F8 gfx950 hazard (#117844)Matt Arsenault
2024-11-25AMDGPU: Handle gfx950 valu write vdst + permlane read hazard (#117287)Matt Arsenault
2024-11-25AMDGPU: Handle vcmpx+permalane gfx950 hazard (#117286)Matt Arsenault
2024-11-25AMDGPU: Refine gfx950 xdl-write-vgpr hazard cases (#117285)Matt Arsenault
2024-11-22AMDGPU: Handle v_mfma_f64_16x16x4_f64 write VGPR read srca/srcb hazard change...Matt Arsenault
2024-11-22AMDGPU: Handle v_mfma_f64_16x16x4_f64 srcc write VGPR hazard change for gfx95...Matt Arsenault
2024-11-22AMDGPU: Handle gfx950 XDL-write-overlapped-smfma-src-c wait state change (#11...Matt Arsenault
2024-11-22AMDGPU: Handle gfx950 change in mfma_f64_16x16x4 + valu hazard (#117262)Matt Arsenault
2024-10-02[AMDGPU] Use the SchedModel available in SIInstrInfo (#110859)Juan Manuel Martinez Caamaño
2024-09-04[AMDGPU] Mitigate GFX12 VALU read SGPR hazard (#100067)Carl Ritson
2024-08-23[AMDGPU] Refactor code for GETPC bundle updates in hazards (NFCI)Carl Ritson
2024-08-22[AMDGPU] Correctly insert s_nops for dst forwarding hazard (#100276)Jeffrey Byrnes
2024-07-23[AMDGPU] Implement workaround for GFX11.5 export priority (#99273)Carl Ritson
2024-07-16[AMDGPU] Use using instead of typedef. NFC.Jay Foad
2024-05-01[AMDGPU] Remove some pointless fallthrough annotationsJay Foad
2024-04-24[CodeGen] Make the parameter TRI required in some functions. (#85968)Xu Zhang
2024-03-31[AMDGPU] Extend MFMA padding option to gfx90a+ (#86768)Austin Kerbow
2024-03-07AMDGPU: Refactor mfma hazard handling [NFC] (#84276)Matt Arsenault
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