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path: root/llvm/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp
AgeCommit message (Expand)Author
2025-11-15Cleanups in AArch64 (#168025)Eric Christopher
2025-11-04[AArch64] Copy implicit def operands when creating LDP. (#164253)David Green
2025-08-12[AArch64] Fix stp kill when merging forward. (#152994)Ricardo Jesus
2025-07-14[AArch64] Remove an unnecessary cast (NFC) (#148763)Kazu Hirata
2025-07-12[AArch64] Remove unnecessary casts (NFC) (#148339)Kazu Hirata
2025-07-11[AArch64] Remove an unused variable (NFC)Jie Fu
2025-07-11[AArch64LoadStoreOpt] BaseReg update is searched also in CF successor (#145583)Sergey Shcherbinin
2025-07-01[AArch64] Fix ldp rename through a bundle (#146415)David Green
2025-06-09[AArch64] Fix a multitude of AArch64 typos (NFC) (#143370)Jonathan Thackray
2025-05-23[NFC][CodeGen] Adopt MachineFunctionProperties convenience accessors (#141101)Rahul Joshi
2025-05-08[AArch64] Merge scaled and unscaled narrow zero stores (#136705)Guy David
2025-04-30[InstrRef] Preserve debug instr num in aarch64-ldst-opt. (#136009)Shubham Sandeep Rastogi
2025-04-24[NFC] [AArch64] Simplify offset scaling in ldst-opt (#137044)Guy David
2025-04-14Reapply "[AArch64][SVE] Pair SVE fill/spill into LDP/STP with -msve-vector-bi...Ricardo Jesus
2025-04-09Revert "[AArch64][SVE] Pair SVE fill/spill into LDP/STP with -msve-vector-bit...David Spickett
2025-04-09[AArch64][SVE] Pair SVE fill/spill into LDP/STP with -msve-vector-bits=128. (...Ricardo Jesus
2025-04-07[NFC][LLVM][AArch64] Cleanup pass initialization for AArch64 (#134315)Rahul Joshi
2024-12-06[AArch64] Fix LDR/STR folding causing memtag failures (#118821)Oliver Stannard
2024-11-27Reland "[AArch64] Define high bits of FPR and GPR registers (take 2) (#114827)"Sander de Smalen
2024-11-22Revert "[AArch64] Define high bits of FPR and GPR registers (take 2) (#114827...Vitaly Buka
2024-11-14[AArch64] Define high bits of FPR and GPR registers (take 2) (#114827)Sander de Smalen
2024-11-11[AArch64] Remove unused includes (NFC) (#115685)Kazu Hirata
2024-09-17[AArch64] Fold UBFMXri to UBFMWri when it's an LSR or LSL alias (#106968)Csanád Hajdú
2024-09-10[AArch64] Prevent the AArch64LoadStoreOptimizer from reordering CFI instructi...Momchil Velikov
2024-08-28[AArch64] Fold more load.x into load.i with large offsetzhongyunde 00443407
2024-08-28[AArch64] Fix buildbot breakage of ubsanzhongyunde 00443407
2024-08-20Revert "[AArch64] Optimize when storing symmetry constants" (#105474)Vitaly Buka
2024-08-20[AArch64] Optimize when storing symmetry constants (#93717)hanbeom
2024-08-16Revert "[AArch64] Fold more load.x into load.i with large offset"Thurston Dang
2024-08-15[AArch64] Fold more load.x into load.i with large offsetzhongyunde 00443407
2024-08-15[AArch64] merge index address with large offset into base addresszhongyunde 00443407
2024-08-02[AArch64] Fix incorrectly getting the destination reg of an insn (#101205)Momchil Velikov
2024-03-17[CodeGen] Use LocationSize for MMO getSize (#84751)David Green
2024-03-06[AArch64] Verify ldp/stp alignment stricter (#84124)Yuta Mukai
2024-03-05Revert "[AArch64] Verify ldp/stp alignment stricter" (#84096)Florian Mayer
2024-03-06[AArch64] Verify ldp/stp alignment stricter (#83948)Yuta Mukai
2024-01-28Revert "[AArch64] merge index address with large offset into base address"David Green
2024-01-11[AArch64LoadStoreOptimizer] Debug messages to track decision making. NFC (#77...Sjoerd Meijer
2023-12-21Revert "[AArch64] Fold more load.x into load.i with large offset"Vitaly Buka
2023-12-21[AArch64] Fold more load.x into load.i with large offsetzhongyunde 00443407
2023-12-21[AArch64] merge index address with large offset into base addresszhongyunde 00443407
2023-11-29[AArch64] Load/store optimizer fixes and cleanup.David Green
2023-11-23[AArch64] Allow LDR merge with same destination register by renaming (#71908)Zhaoxuan Jiang
2023-11-11[llvm] Stop including llvm/ADT/BitVector.h (NFC)Kazu Hirata
2023-11-02[AArch64] Only clear kill flags if necessary when merging str (#69680)Zhaoxuan Jiang
2023-10-30[AArch64] Use TargetRegisterClass::hasSubClassEq in tryToFindRegisterToRenameCullen Rhodes
2023-09-22Reapply "[AArch64] Merge LDRSWpre-LD[U]RSW pair into LDPSWpre"Zhuojia Shen
2023-09-14[AArch64] New subtarget features to control ldp and stp formation (#66098)Manos Anagnostakis
2023-07-26Revert "[AArch64] Merge LDRSWpre-LD[U]RSW pair into LDPSWpre"Alexander Kornienko
2023-07-18[AArch64] Merge LDRSWpre-LD[U]RSW pair into LDPSWpreZhuojia Shen
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