| Age | Commit message (Expand) | Author |
|---|
| 2025-11-20 | [AArch64][PAC] Use enum to describe LR signing condition (NFC) (#168548) | Anatoly Trosinenko |
| 2025-11-18 | [AArch64] Treat COPY between cross-register banks as expensive (#167661) | Guy David |
| 2025-11-14 | [AArch64][FEAT_CMPBR] Codegen for Armv9.6-a CBB and CBH (#164899) | David Tellenbach |
| 2025-11-14 | [AArch64][DebugInfo]Add Target hooks for InstrRef on AArch64 (#165953) | Shubham Sandeep Rastogi |
| 2025-11-13 | [AArch64] Generalize CSEL a, b, cc, SUBS(SUB(x,y), 0) -> CSEL a, b, cc, SUBS... | AZero13 |
| 2025-11-10 | CodeGen: Remove TRI arguments from stack load/store hooks (#158240) | Matt Arsenault |
| 2025-11-10 | CodeGen: Remove TRI argument from getRegClass (#158225) | Matt Arsenault |
| 2025-11-10 | CodeGen: Keep reference to TargetRegisterInfo in TargetInstrInfo (#158224) | Matt Arsenault |
| 2025-11-10 | [AArch64] Allow peephole to optimize AND + signed compare with 0 (#153608) | AZero13 |
| 2025-11-10 | [MachineOutliner] Don't outline ADRP pair to avoid incorrect ICF (#160232) | Pranav Kant |
| 2025-11-06 | AArch64: support extended spills in SEH on WoS (#166849) | Saleem Abdulrasool |
| 2025-10-29 | [AArch64][PAC] Fix an implicit pointer-to-bool conversion (#165056) | Jon Roelofs |
| 2025-10-25 | [AArch64] Widen GPR32 zero cycle zeroing (#164244) | Tomer Shafir |
| 2025-10-20 | [AArch64] Convert `CSEL(X, 1)` into `CSINC(X, XZR)` in early-ifcvt (#162993) | Csanád Hajdú |
| 2025-10-20 | [AArch64] Improve lowering of GPR zeroing in copyPhysReg (#163059) | Tomer Shafir |
| 2025-10-16 | Return nullopt if Reg is undef. (#155893) | Shubham Sandeep Rastogi |
| 2025-10-12 | [AArch64][NFC] Use member variable RI instead getRegisterInfo in copyPhysReg ... | Tomer Shafir |
| 2025-10-06 | [AArch64][SME] Remove support for `-arch64-enable-zpr-predicate-spills` (#161... | Benjamin Maxwell |
| 2025-10-06 | [NFC][AArch64] Flatten a branch on AArch64InstrInfo::copyPhysReg (#161138) | Tomer Shafir |
| 2025-10-02 | [Codegen] Add a separate stack ID for scalable predicates (#142390) | Benjamin Maxwell |
| 2025-10-02 | [AArch64] Combine PTEST_FIRST(PTRUE, CONCAT(A, B)) -> PTEST_FIRST(PTRUE, A) (... | Kerry McLaughlin |
| 2025-09-16 | [AArch64] Unfold adds when eliminating frame index with scalable offset (#158... | Hongyu Chen |
| 2025-09-12 | CodeGen: Remove MachineFunction argument from getRegClass (#158188) | Matt Arsenault |
| 2025-09-11 | [AArch64] Verify OPERAND_SHIFT_MSL and OPERAND_IMPLICIT_IMM_0 (#157031) | David Green |
| 2025-09-11 | [AArch64][SVE2p1] Remove redundant PTESTs when predicate is a WHILEcc_x2 (#15... | Kerry McLaughlin |
| 2025-09-10 | [AArch64] Lower zero cycle FPR zeroing (#156261) | Tomer Shafir |
| 2025-09-09 | [AArch64][SVE] Add PTEST_FIRST pseudo instruction (#157489) | Kerry McLaughlin |
| 2025-09-08 | CodeGen: Pass SubtargetInfo to TargetGenInstrInfo constructors (#157337) | Matt Arsenault |
| 2025-08-30 | [AArch64] Remove an unnecessary cast (NFC) (#156139) | Kazu Hirata |
| 2025-08-28 | [AArch64] Split zero cycle zeoring per register class (#154561) | Tomer Shafir |
| 2025-08-28 | [AArch64] Lower FPR register moves to zero cycle NEON (#153158) | Tomer Shafir |
| 2025-08-20 | [AArch64][SME] Rework VG CFI information for streaming-mode changes (#152283) | Benjamin Maxwell |
| 2025-08-19 | [AArch64] Fix zero-register copying with zero-cycle moves (#154362) | David Tellenbach |
| 2025-08-18 | [AArch64] Replace SmallSet with SmallPtrSet (NFC) (#154264) | Kazu Hirata |
| 2025-08-18 | [AArch64][MachineCombiner] Combine sequences of gather patterns (#152979) | Jonathan Cohen |
| 2025-08-14 | [AArch64] Fix ‘>= 0’ is always true warning. NFC | David Green |
| 2025-08-06 | Fix MSVC truncation to char warning. NFC. | Simon Pilgrim |
| 2025-08-06 | [AArch64][SVE] Tweak how SVE CFI expressions are emitted (#151677) | Benjamin Maxwell |
| 2025-07-29 | [AArch64] Remove `UnsafeFPMath` (#150876) | paperchalice |
| 2025-07-25 | Revert "[AArch64][Machine-Combiner] Split gather patterns into neon regs to m... | Jonathan Cohen |
| 2025-07-24 | [AArch64] Predicate should be NE for CBNZW (#150287) | AZero13 |
| 2025-07-17 | [AArch64][Machine-Combiner] Split gather patterns into neon regs to multiple ... | Jonathan Cohen |
| 2025-07-16 | [MachineOutliner] Avoid ranges that cross bundle boundary (#148977) | Ellis Hoag |
| 2025-07-16 | [LLVM][AArch64InstrInfo] Prevent fill folding when DstReg is SP. (#148885) | Paul Walker |
| 2025-07-15 | [AArch64] Use correct regclass for spills of ZPR2/ZPR4 (#148806) | Sander de Smalen |
| 2025-07-11 | [AArch64] Use mov imm pseudo instructions in madd combine. (#147510) | David Green |
| 2025-06-30 | [MachineOutliner] Remove LOHs from outlined candidates (#143617) | Ellis Hoag |
| 2025-06-28 | [AArch64] Align 0-cycle reg-mov model of GPR64, GPR32 reg classes (#146051) | Tomer Shafir |
| 2025-06-26 | [AArch64] Use 0-cycle reg2reg MOVs for FPR32, FPR16, FPR8 (#144152) | Tomer Shafir |
| 2025-06-09 | [AArch64] Fix a multitude of AArch64 typos (NFC) (#143370) | Jonathan Thackray |
