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path: root/llvm/test/CodeGen/AMDGPU/llvm.mulo.ll
AgeCommit message (Expand)Author
2025-07-23[RFC][NFC][AMDGPU] Remove `-verify-machineinstrs` from `llvm/test/CodeGen/AMD...Shilei Tian
2025-06-27[AMDGPU] Fix bad removal of s_delay_alu (#145728)Ana Mihajlovic
2025-04-10Reapply [AMDGPU] SIFixSgprCopies should not process twice VGPR to SGPR copies...alex-t
2025-04-10Revert "[AMDGPU] SIFixSgprCopies should not process twice VGPR to SGPR copies...Nico Weber
2025-04-10[AMDGPU] SIFixSgprCopies should not process twice VGPR to SGPR copies inserte...alex-t
2025-03-28[AMDGPU] Unused sdst writing to null (#133229)Ana Mihajlovic
2025-03-18AMDGPU: Move insertion into V2SCopies map (#130776)Matt Arsenault
2025-03-13Reland "[AMDGPU] Remove s_delay_alu for VALU->SGPR->SALU (#127212)" (#131111)Ana Mihajlovic
2025-03-13AMDGPU: Replace ptr addrspace(1) undefs with poison (#130900)Matt Arsenault
2025-03-12Revert "[AMDGPU] Remove s_delay_alu for VALU->SGPR->SALU (#127212)"Kazu Hirata
2025-03-12[AMDGPU] Remove s_delay_alu for VALU->SGPR->SALU (#127212)Ana Mihajlovic
2025-01-30PeepholeOpt: Do not add subregister indexes to reg_sequence operands (#124111)Matt Arsenault
2025-01-30[AMDGPU] Rewrite GFX12 SGPR hazard handling to dedicated pass (#118750)Carl Ritson
2024-11-08Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#...Shilei Tian
2024-11-08Revert "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#1...Shilei Tian
2024-11-08[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)Shilei Tian
2024-10-21[AMDGPU] Skip VGPR deallocation for waveslot limited kernels (#112765)Stanislav Mekhanoshin
2024-07-23[AMDGPU] Codegen support for constrained multi-dword sloads (#96163)Christudasan Devadasan
2024-07-15Reapply "AMDGPU: Move attributor into optimization pipeline (#83131)" and fol...Matt Arsenault
2024-07-14Revert "AMDGPU: Move attributor into optimization pipeline (#83131)" and foll...dyung
2024-07-14AMDGPU: Move attributor into optimization pipeline (#83131)Matt Arsenault
2024-01-18[AMDGPU] CodeGen for GFX12 S_WAIT_* instructions (#77438)Jay Foad
2024-01-17[AMDGPU] Disable V_MAD_U64_U32/V_MAD_I64_I32 workaround for GFX12 (#77927)Jay Foad
2024-01-16[AMDGPU,test] Change llc -march= to -mtriple= (#75982)Fangrui Song
2023-12-14[AMDGPU] Enable GCNRewritePartialRegUses pass by default. (#72975)Valery Pykhtin
2023-07-19[AMDGPU] Insert s_nop before s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)Jay Foad
2023-07-04[AMDGPU] Do not wait for vscnt on function entry and returnJay Foad
2023-06-07[AMDGPU] Turn off pass to rewrite partially used virtual superregisters after...Valery Pykhtin
2023-05-26[AMDGPU] Add pass to rewrite partially used virtual superregisters after Rena...Valery Pykhtin
2022-11-29AMDGPU: Bulk update some generic intrinsic tests to opaque pointersMatt Arsenault
2022-11-29[DAG] Attempt to replace a mul node with an existing umul_lohi/smul_lohi node...Simon Pilgrim
2022-09-15[AMDGPU] Always select s_cselect_b32 for uniform 'select' SDNodeAlexander Timofeev
2022-07-05[AMDGPU] gfx11 Generate VOPD InstructionsJoe Nash
2022-06-30[AMDGPU] GFX11: automatically release VGPRs at the end of the shaderJay Foad
2022-06-29[AMDGPU] New AMDGPUInsertDelayAlu passJay Foad
2022-06-16[AMDGPU] Change use null for dead sdst to be gfx1030+David Stuttard
2022-06-13[AMDGPU] Use null for dead sdst operandStanislav Mekhanoshin
2022-06-13[AMDGPU] Fix GFX11 codegen for V_MAD_U64_U32 and V_MAD_I64_I32Jay Foad
2022-01-11Revert D109159 : Revert "[amdgpu] Enable selection of `s_cselect_b64`."David Salinas
2022-01-05Revert "Revert D109159 "[amdgpu] Enable selection of `s_cselect_b64`.""Nico Weber
2022-01-05Revert D109159 "[amdgpu] Enable selection of `s_cselect_b64`."David Salinas
2021-11-24[AMDGPU] Implement widening multiplies with v_mad_i64_i32/v_mad_u64_u32Jay Foad
2021-11-23[AMDGPU] Fix the name of a test caseJay Foad
2021-11-19[AMDGPU] Use new opcode for indexed vgpr readsJay Foad
2021-09-14[AMDGPU] Switch PostRA sched to MachineSchedJoe Nash
2021-09-07[amdgpu] Enable selection of `s_cselect_b64`.Michael Liao
2021-08-25[AMDGPU] Divergence-driven compare operations instruction selectionalex-t
2021-04-26[AMDGPU] Experiments show that the GCNRegBankReassign pass significantly impactsBaptiste Saleil
2021-04-01[AMDGPU][MC][GFX10][GFX90A] Corrected _e32/_e64 sufficesDmitry Preobrazhensky
2021-03-29[AMDGPU] Extend gfx10 test coverage. NFC.Petar Avramovic
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