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path: root/llvm/test/CodeGen/AMDGPU/insert_vector_elt.ll
AgeCommit message (Expand)Author
2025-11-10RegisterCoalescer: Enable terminal rule by default for AMDGPU (#161621)Matt Arsenault
2025-06-11Reland "[SelectionDAG] Make `(a & x) | (~a & y) -> (a & (x ^ y)) ^ y` availab...Iris Shi
2025-06-11Revert "[SelectionDAG] Make `(a & x) | (~a & y) -> (a & (x ^ y)) ^ y` availab...Iris Shi
2025-06-09[SelectionDAG] Make `(a & x) | (~a & y) -> (a & (x ^ y)) ^ y` available for a...Iris Shi
2025-06-05MachineScheduler: Improve instruction clustering (#137784)Ruiling, Song
2025-05-28MachineScheduler: Reset next cluster candidate for each node (#139513)Ruiling, Song
2025-03-25[AMDGPU][SelectionDAG] Use COPY instead of S_MOV_B32 to assign values to M0 (...Juan Manuel Martinez Caamaño
2025-03-14AMDGPU: Replace ptr addrspace(4) undef uses with poison in tests (#131095)Matt Arsenault
2025-03-13AMDGPU: Replace some float undef test uses with poison (#131090)Matt Arsenault
2025-03-13AMDGPU: Replace <8 x i32> undef uses in tests with poison (#130903)Matt Arsenault
2025-03-12AMDGPU: Replace insertelement poison with insertelement undef (#130896)Matt Arsenault
2025-02-22PeepholeOpt: Allow introducing subregister uses on reg_sequence (#127052)Matt Arsenault
2024-11-26AMDGPU: Remove some -verify-machineinstrs from tests (#117736)Matt Arsenault
2024-11-08Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#...Shilei Tian
2024-11-08Revert "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#1...Shilei Tian
2024-11-08[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)Shilei Tian
2024-09-19[AMDGPU] Promote uniform ops to I32 in DAGISel (#106383)Pierre van Houtryve
2024-07-15Reapply "AMDGPU: Move attributor into optimization pipeline (#83131)" and fol...Matt Arsenault
2024-07-14Revert "AMDGPU: Move attributor into optimization pipeline (#83131)" and foll...dyung
2024-07-14AMDGPU: Move attributor into optimization pipeline (#83131)Matt Arsenault
2023-10-30[AMDGPU] Select 64-bit imm moves if can be encoded as 32 bit operand (#70395)Stanislav Mekhanoshin
2023-05-26Rewrite load-store-vectorizer.Justin Lebar
2023-04-14[AMDGPU] Less aggressively break large PHIspvanhout
2023-03-28[AMDGPU] Break-up large PHIs for DAGISelpvanhout
2022-12-19AMDGPU: Update some tests to use opaque pointersMatt Arsenault
2022-11-29[AMDGPU] Add support for new LLVM vector typesMateja Marjanovic
2022-10-29[DAG] Enable combineShiftOfShiftedLogic folds after type legalizationSimon Pilgrim
2022-10-04[AMDGPU][DAG] Fix insert_vector_elt lowering for 8 bit elementsPierre van Houtryve
2022-09-28AMDGPU: Make various vector undefs legalMatt Arsenault
2022-09-15[AMDGPU] Always select s_cselect_b32 for uniform 'select' SDNodeAlexander Timofeev
2022-07-30[AMDGPU] Extend SILoadStoreOptimizer to s_load instructionsCarl Ritson
2022-06-02[AMDGPU] Improve codegen of extractelement/insertelement in some casesJulien Pages
2022-05-18[AMDGPU] Aggressively fold immediates in SIShrinkInstructionsJay Foad
2022-05-18[AMDGPU] Aggressively fold immediates in SIFoldOperandsJay Foad
2022-02-01[StructurizeCFG] Clean up some boolean not instructionsJay Foad
2022-01-31Revert "[Local] invertCondition: try modifying an existing ICmpInst"Jay Foad
2022-01-31[Local] invertCondition: try modifying an existing ICmpInstJay Foad
2022-01-11Revert D109159 : Revert "[amdgpu] Enable selection of `s_cselect_b64`."David Salinas
2022-01-05Revert "Revert D109159 "[amdgpu] Enable selection of `s_cselect_b64`.""Nico Weber
2022-01-05Revert D109159 "[amdgpu] Enable selection of `s_cselect_b64`."David Salinas
2021-12-01[AMDGPU] Set most sched model resource's BufferSize to oneAustin Kerbow
2021-11-20[AMDGPU] Do not generate ELF symbols for the local branch target labelsRamNalamothu
2021-09-14[AMDGPU] Switch PostRA sched to MachineSchedJoe Nash
2021-09-07[amdgpu] Enable selection of `s_cselect_b64`.Michael Liao
2021-08-25[AMDGPU] Divergence-driven compare operations instruction selectionalex-t
2021-08-10AMDGPU: Add alloc priority to global rangesMatt Arsenault
2021-08-05[AMDGPU] Improve v2i32/v2f32 insertelt patternsStanislav Mekhanoshin
2021-08-05[AMDGPU] add v2i32 and v2f32 insert_vector_elt tests. NFC.Stanislav Mekhanoshin
2021-06-30[AMDGPU] Add S_MOV_B64_IMM_PSEUDO for wide constantsStanislav Mekhanoshin
2021-06-24[AMDGPU] Add 224-bit vector types and link 192-bit types to MVTsCarl Ritson
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