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path: root/llvm/test/CodeGen/AMDGPU/fshr.ll
AgeCommit message (Expand)Author
2025-11-11[AMDGPU] Add pattern to select scalar ops for fshr with uniform operands (#16...Akash Dutta
2025-09-11[AMDGPU][SDAG] Legalise v2i32 or/xor/and instructions to make use of 64-bit w...Chris Jackson
2025-07-23[RFC][NFC][AMDGPU] Remove `-verify-machineinstrs` from `llvm/test/CodeGen/AMD...Shilei Tian
2025-03-26[AMDGPU][True16][CodeGen] srl pattern for true16 mode (#132987)Brox Chen
2025-03-12[AMDGPU][True16] added Pre-RA hint to improve copy elimination (#103366)Brox Chen
2025-03-04[AMDGPU][True16][CodeGen] fshr true16 pattern (#129085)Brox Chen
2024-11-08Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#...Shilei Tian
2024-11-08Revert "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#1...Shilei Tian
2024-11-08[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)Shilei Tian
2024-10-21[AMDGPU] Skip VGPR deallocation for waveslot limited kernels (#112765)Stanislav Mekhanoshin
2024-08-02Revert "[AMDGPU] Always lower s/udiv64 by constant to MUL (#100723)"Fangrui Song
2024-08-02[AMDGPU] Always lower s/udiv64 by constant to MUL (#100723)Pierre van Houtryve
2024-07-23[AMDGPU][SILoadStoreOptimizer] Merge constrained sloads (#96162)Christudasan Devadasan
2024-07-15Reapply "AMDGPU: Move attributor into optimization pipeline (#83131)" and fol...Matt Arsenault
2024-07-14Revert "AMDGPU: Move attributor into optimization pipeline (#83131)" and foll...dyung
2024-07-14AMDGPU: Move attributor into optimization pipeline (#83131)Matt Arsenault
2024-06-14[AMDGPU] Adding multiple use analysis to SIPeepholeSDWA (#94800)Brian Favela
2024-01-16[AMDGPU,test] Change llc -march= to -mtriple= (#75982)Fangrui Song
2023-07-19[AMDGPU] Insert s_nop before s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)Jay Foad
2023-07-04[AMDGPU] Do not wait for vscnt on function entry and returnJay Foad
2022-12-29[TargetLowering] Teach BuildUDIV to take advantage of leading zeros in the di...Craig Topper
2022-11-29AMDGPU: Convert some bit operation tests to opaque pointersMatt Arsenault
2022-10-03[AMDGPU] Use V_PERM to match buildvectors when inputs are not canonicalized (...jeff
2022-07-30[AMDGPU] Extend SILoadStoreOptimizer to s_load instructionsCarl Ritson
2022-07-28[DAG] Enable ISD::SRL SimplifyMultipleUseDemandedBits handling inside Simplif...Simon Pilgrim
2022-07-08[AMDGPU] Add GFX11 test coverageJay Foad
2022-05-18[AMDGPU] Aggressively fold immediates in SIShrinkInstructionsJay Foad
2022-05-18[AMDGPU] Aggressively fold immediates in SIFoldOperandsJay Foad
2022-05-06[SelectionDAG] Clear promoted bits before UREM on shift amount in PromoteIntR...Craig Topper
2022-03-09[AMDGPU] Move call clobbered return address registers s[30:31] to callee save...Venkata Ramanaiah Nalamothu
2022-01-26[LSV] Vectorize loads of vectors by turning it into a larger vectorBenjamin Kramer
2021-12-22Revert "[AMDGPU] Move call clobbered return address registers s[30:31] to cal...Ron Lieberman
2021-12-22[AMDGPU] Move call clobbered return address registers s[30:31] to callee save...RamNalamothu
2021-12-01[AMDGPU] Set most sched model resource's BufferSize to oneAustin Kerbow
2021-10-26[AMDGPU] Add constrained shift pattern matches.Abinav Puthan Purayil
2021-09-14[AMDGPU] Switch PostRA sched to MachineSchedJoe Nash
2021-04-26[AMDGPU] Experiments show that the GCNRegBankReassign pass significantly impactsBaptiste Saleil
2021-04-01[AMDGPU][MC][GFX10][GFX90A] Corrected _e32/_e64 sufficesDmitry Preobrazhensky
2021-03-29[AMDGPU] Extend gfx10 test coverage. NFC.Petar Avramovic
2021-01-26[AMDGPU] Update subtarget features for new target ID supportAustin Kerbow
2021-01-05[NFC] Removed unused prefixes in test/CodeGen/AMDGPUMircea Trofin
2020-11-16AMDGPU: Select global saddr mode from SGPR pointerMatt Arsenault
2020-11-01[AMDGPU] Add alignment check for v3 to v4 load type promotionChristudasan Devadasan
2020-09-16AMDGPU: Improve <2 x i24> arguments and return value handlingMatt Arsenault
2020-09-14[AMDGPU] Don't cluster storesJay Foad
2020-08-21[SelectionDAG] Better legalization for FSHL and FSHRJay Foad
2020-08-09Fix 64-bit copy to SCCPiotr Sobczak
2020-08-07[Scheduling] Create the missing dependency edges for store clusterQingShan Zhang
2020-08-02[AMDGPU] Regenerate tests to fix whitespace indentationsSimon Pilgrim
2020-07-30[AMDGPU/MemOpsCluster] Clean-up fixme's around mem ops clustering logichsmahesha
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