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path: root/llvm/test/CodeGen/AMDGPU/control-flow-fastregalloc.ll
AgeCommit message (Expand)Author
2025-07-23[RFC][NFC][AMDGPU] Remove `-verify-machineinstrs` from `llvm/test/CodeGen/AMD...Shilei Tian
2025-03-13AMDGPU: Replace ptr addrspace(3) undef in tests with poison (#131049)Matt Arsenault
2025-03-04DAG: Use phi to create vregs instead of the constant input (#129464)Matt Arsenault
2024-10-08[AMDGPU] Include WWM register spill into BB Prolog (#111496)Christudasan Devadasan
2024-09-30[AMDGPU] Split vgpr regalloc pipeline (#93526)Christudasan Devadasan
2024-03-06[AMDGPU] Rename COV module flag to amdhsa_code_object_version (#79905)Emma Pilkington
2024-02-09[AMDGPU] Don't fix the scavenge slot at offset 0 (#79136)Diana Picus
2023-10-27[AMDGPU] Try to fix the block prologs broken by RA inserted instructions (#69...Christudasan Devadasan
2023-09-21[AMDGPU] Remove Code Object V2 (#65715)Pierre van Houtryve
2023-09-11[test] Change llc -march= to -mtriple=Fangrui Song
2023-07-31Reapply "[CodeGen]Allow targets to use target specific COPY instructions for ...Matt Arsenault
2023-07-26Revert "[CodeGen]Allow targets to use target specific COPY instructions for l...Vitaly Buka
2023-07-07[AMDGPU][SILowerSGPRSpills] Spill SGPRs to virtual VGPRsChristudasan Devadasan
2023-04-10[AMDGPU] Introduce SIInstrWorklist to process instructions in moveToVALUskc7
2023-02-02AMDGPU: Use module flag to get code object version at IR levelChangpeng Fang
2022-12-21Revert "[AMDGPU][SILowerSGPRSpills] Spill SGPRs to virtual VGPRs"Christudasan Devadasan
2022-12-19[AMDGPU] Convert some tests to opaque pointers (NFC)Nikita Popov
2022-12-17[AMDGPU][SILowerSGPRSpills] Spill SGPRs to virtual VGPRsChristudasan Devadasan
2022-08-20(Reland) [fastalloc] Support allocating specific register class in fastallocLuo, Yuanke
2022-08-15Revert "(Reland) [fastalloc] Support allocating specific register class in fa...Luo, Yuanke
2022-08-13(Reland) [fastalloc] Support allocating specific register class in fastallocLuo, Yuanke
2022-06-23Revert "[fastalloc] Support allocating specific register class in fastalloc"Nico Weber
2022-06-23[fastalloc] Support allocating specific register class in fastallocLuo, Yuanke
2022-02-18[CodeGen] Remove unneeded regex escaping in FileCheck patterns. NFC.Jay Foad
2021-11-20[AMDGPU] Do not generate ELF symbols for the local branch target labelsRamNalamothu
2021-07-15[AMDGPU] Refine -O0 and -O1 passes.Stanislav Mekhanoshin
2021-04-12[AMDGPU] Save VGPR of whole wave when spillingSebastian Neubauer
2020-10-20[AMDGPU] Remove fix up operand from SI_ELSECarl Ritson
2020-10-14AMDGPU: Update AMDHSA code object version handlingKonstantin Zhuravlyov
2020-09-30Reapply "RegAllocFast: Rewrite and improve"Matt Arsenault
2020-09-22Revert "Reapply Revert "RegAllocFast: Rewrite and improve""Muhammad Omair Javaid
2020-09-21Reapply Revert "RegAllocFast: Rewrite and improve"Matt Arsenault
2020-09-18Temporarily Revert "RegAllocFast: Rewrite and improve"Eric Christopher
2020-09-18RegAllocFast: Rewrite and improveMatt Arsenault
2020-09-03AMDGPU: Remove code to handle tied si_else operandsMatt Arsenault
2020-06-03[AMDGPU] Make SGPR spills exec mask agnosticCarl Ritson
2020-04-06[AMDGPU] Disable 'Skip Uniform Regions' optimization by default for AMDGPU.Konstantin Pyzhov
2020-04-06Revert e1730cfeb3588f20dcf4a96b181ad52761666e52Konstantin Pyzhov
2020-04-06[AMDGPU] Disable 'Skip Uniform Regions' optimization by default for AMDGPU.Konstantin Pyzhov
2020-03-19[AMDGPU] Add Scratch Wave Offset to Scratch Buffer Descriptor in entry functionsScott Linder
2020-01-22Resubmit: [AMDGPU] Invert the handling of skip insertion.cdevadas
2020-01-21Revert "[AMDGPU] Invert the handling of skip insertion."Nicolai Hähnle
2020-01-15[AMDGPU] Invert the handling of skip insertion.cdevadas
2019-10-14[AMDGPU] Come back patch for the 'Assign register class for cross block value...Alexander Timofeev
2019-06-06[AMDGPU] Partial revert for the ba447bae7448435c9986eece0811da1423972fddAlexander Timofeev
2019-05-26 [AMDGPU] Divergence driven ISel. Assign register class for cross block va...Alexander Timofeev
2019-05-25Revert r361644, "[AMDGPU] Divergence driven ISel. Assign register class for c...Peter Collingbourne
2019-05-24[AMDGPU] Divergence driven ISel. Assign register class for cross block values...Alexander Timofeev
2018-11-07RegAllocFast: Leave unassigned virtreg entries in mapMatthias Braun
2018-09-11[AMDGPU] Preliminary patch for divergence driven instruction selection. Immed...Alexander Timofeev
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