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path: root/llvm/test/CodeGen/AMDGPU/collapse-endcf.ll
AgeCommit message (Expand)Author
2025-11-21AMDGPU: Stop implementing shouldCoalesce (#168988)Matt Arsenault
2025-11-20RenameIndependentSubregs: try to only implicit def used subregs (#167486)Carl Ritson
2025-11-14AMDGPU: Use v_mov_b32 to implement divergent zext i32->i64 (#168166)Matt Arsenault
2025-08-27[AMDGPU] Prevent generation of unused SGPR IMPLICIT_DEF assignments (#155241)Chris Jackson
2025-07-23[RFC][NFC][AMDGPU] Remove `-verify-machineinstrs` from `llvm/test/CodeGen/AMD...Shilei Tian
2025-04-24AMDGPU: Remove amdhsa_code_object_version module flags from most tests (#136363)Matt Arsenault
2025-03-14AMDGPU: Replace test uses of ptr addrspace(5) undef with poison (#131101)Matt Arsenault
2025-03-12AMDGPU: Replace insertelement poison with insertelement undef (#130896)Matt Arsenault
2025-03-04DAG: Use phi to create vregs instead of the constant input (#129464)Matt Arsenault
2024-11-12[AMDGPU] Skip non-wwm reg implicit-def from bb prolog (#115834)Christudasan Devadasan
2024-11-08Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#...Shilei Tian
2024-11-08Revert "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#1...Shilei Tian
2024-11-08[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)Shilei Tian
2024-10-21[AMDGPU]: Add implicit-def to the BB prolog (#112872)Christudasan Devadasan
2024-10-08[AMDGPU] Include WWM register spill into BB Prolog (#111496)Christudasan Devadasan
2024-09-30[AMDGPU] Split vgpr regalloc pipeline (#93526)Christudasan Devadasan
2024-09-25[AMDGPU] Do not count implicit VGPRs in SIInsertWaitcnts (#109049)Stanislav Mekhanoshin
2024-09-14[AMDGPU] Avoid unneeded waitcounts before spill stores (#108303)Stanislav Mekhanoshin
2024-07-15Reapply "AMDGPU: Move attributor into optimization pipeline (#83131)" and fol...Matt Arsenault
2024-07-14Revert "AMDGPU: Move attributor into optimization pipeline (#83131)" and foll...dyung
2024-07-14AMDGPU: Move attributor into optimization pipeline (#83131)Matt Arsenault
2024-03-06[AMDGPU] Rename COV module flag to amdhsa_code_object_version (#79905)Emma Pilkington
2024-02-09[AMDGPU] Don't fix the scavenge slot at offset 0 (#79136)Diana Picus
2024-01-16[AMDGPU,test] Change llc -march= to -mtriple= (#75982)Fangrui Song
2023-12-12[AMDGPU][NFC] Test autogenerated llc tests for COV5 (#74339)Saiyedul Islam
2023-10-29[DAG] Attempt shl narrowing in SimplifyDemandedBits (REAPPLIED)Simon Pilgrim
2023-10-27[AMDGPU] Try to fix the block prologs broken by RA inserted instructions (#69...Christudasan Devadasan
2023-10-04Revert "[DAG] Attempt shl narrowing in SimplifyDemandedBits"Kirill Stoimenov
2023-10-04[DAG] Attempt shl narrowing in SimplifyDemandedBitsSimon Pilgrim
2023-09-29[AMDGPU] Introduce AMDGPU::SGPR_SPILL asm comment flag (#67091)Yashwant Singh
2023-09-12Revert "[AMDGPU] Make default AMDHSA Code Object Version to be 5 (#65410)" (#...Saiyedul Islam
2023-09-12[AMDGPU] Make default AMDHSA Code Object Version to be 5 (#65410)Saiyedul Islam
2023-07-31Reapply "[CodeGen]Allow targets to use target specific COPY instructions for ...Matt Arsenault
2023-07-26Revert "[CodeGen]Allow targets to use target specific COPY instructions for l...Vitaly Buka
2023-07-07[AMDGPU][SILowerSGPRSpills] Spill SGPRs to virtual VGPRsChristudasan Devadasan
2023-06-08AMDGPU: Don't run AMDGPUAttributor with -O0Matt Arsenault
2023-05-16[MachineSink] Don't reject sinking because of dead def in isProfitableToSinkT...Jonas Paulsson
2023-03-28[AMDGPU] Break-up large PHIs for DAGISelpvanhout
2023-03-01[InstCombine] Improvement the analytics through the dominating conditionZhongyunde
2023-02-28[AMDGPU] Update the CHECK autogenerated as it's expiredzhongyunde
2022-12-21Revert "[AMDGPU][SILowerSGPRSpills] Spill SGPRs to virtual VGPRs"Christudasan Devadasan
2022-12-19[AMDGPU] Convert some tests to opaque pointers (NFC)Nikita Popov
2022-12-17[AMDGPU][SILowerSGPRSpills] Spill SGPRs to virtual VGPRsChristudasan Devadasan
2022-08-20(Reland) [fastalloc] Support allocating specific register class in fastallocLuo, Yuanke
2022-08-15Revert "(Reland) [fastalloc] Support allocating specific register class in fa...Luo, Yuanke
2022-08-13(Reland) [fastalloc] Support allocating specific register class in fastallocLuo, Yuanke
2022-07-21[AMDGPU] Combine s_or_saveexec, s_xor instructions.Thomas Symalla
2022-06-23Revert "[fastalloc] Support allocating specific register class in fastalloc"Nico Weber
2022-06-23[fastalloc] Support allocating specific register class in fastallocLuo, Yuanke
2022-01-18[AMDGPU] Disable optimizeEndCf at -O0Christudasan Devadasan
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