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path: root/llvm/test/CodeGen/AMDGPU/bf16.ll
AgeCommit message (Expand)Author
2025-11-21[AMDGPU] Enable multi-group xnack replay in hardware (GFX1250) (#169016)Christudasan Devadasan
2025-11-13[AMDGPU][SIInsertWaitCnts] Gfx12.5 - Refactor xcnt optimization (#164357)Ryan Mitchell
2025-11-11[AMDGPU] Add pattern to select scalar ops for fshr with uniform operands (#16...Akash Dutta
2025-11-06Reland: CodeGen: Record MMOs in finalizeBundle (#166689)Nicolai Hähnle
2025-11-05Revert "CodeGen: Record MMOs in finalizeBundle" (#166520)Jan Patrick Lehr
2025-11-05CodeGen: Record MMOs in finalizeBundle (#166210)Nicolai Hähnle
2025-10-23[AMDGPU] Change patterns for v_[pk_]add_{min|max} (#164881)Stanislav Mekhanoshin
2025-10-21[AMDGPU] Add clamp support to v_add_{max|min}_{i|u}32 (#164489)Stanislav Mekhanoshin
2025-10-11Fix legalizing `FNEG` and `FABS` with `TypeSoftPromoteHalf` (#156343)beetrees
2025-10-07[AMDGPU] Use true16 loads with +real-true16 and sram-ecc (#161256)Stanislav Mekhanoshin
2025-10-03[AMDGPU] Enable XNACK on gfx1250 (#161457)Shilei Tian
2025-09-28[AMDGPU] Regenerate checks for test/CodeGen/AMDGPU/bf16.ll (#161069)macurtis-amd
2025-09-25[AMDGPU] Fix vector legalization for bf16 valu ops (#158439)Giuseppe Rossini
2025-09-23[AMDGPU] Add gfx1250 runline to bf16.ll. NFC (#160241)Stanislav Mekhanoshin
2025-09-09[AMDGPU][True16][CodeGen] update isel pattern with vgpr16 for 16 bit types (#...Brox Chen
2025-09-04[AMDGPU][True16][Codegen] remove another build_vector pattern from true16 (#1...Brox Chen
2025-08-20[AMDGPU][True16][CodeGen] use vgpr16 for zext patterns (reopen #153894) (#154...Brox Chen
2025-08-18Revert "[AMDGPU][True16][CodeGen] use vgpr16 for zext patterns (#1538… (#15...Brox Chen
2025-08-18[AMDGPU][True16][CodeGen] use vgpr16 for zext patterns (#153894)Brox Chen
2025-08-08[AMDGPU] Removed extra blank lines from tests. NFC. (#152612)Stanislav Mekhanoshin
2025-08-07[AMDGPU] Enable CodeGen for v_pk_fma_bf16 (#152578)Stanislav Mekhanoshin
2025-07-25[AMDGPU] Allocate AVRegClass last (#146606)Jeffrey Byrnes
2025-07-21[AMDGPU][NFC] Run the general bf16 tests for GFX950. (#149796)Ivan Kosarev
2025-07-18[AMDGPU][True16][Codegen] remove packed build_vector pattern from true16 (#14...Brox Chen
2025-06-05MachineScheduler: Improve instruction clustering (#137784)Ruiling, Song
2025-05-30AMDGPU: Move bf16 copysign tests to separate file (#142114)Matt Arsenault
2025-05-28MachineScheduler: Reset next cluster candidate for each node (#139513)Ruiling, Song
2025-05-05[AMDGPU] SIPeepholeSDWA: Handle V_CNDMASK_B32_e64 (#137930)Frederik Harwath
2025-04-10Reapply [AMDGPU] SIFixSgprCopies should not process twice VGPR to SGPR copies...alex-t
2025-04-10Revert "[AMDGPU] SIFixSgprCopies should not process twice VGPR to SGPR copies...Nico Weber
2025-04-10[AMDGPU] SIFixSgprCopies should not process twice VGPR to SGPR copies inserte...alex-t
2025-04-10[CodeGen] Simplify expandRoundInexactToOdd (#134988)Jay Foad
2025-04-02[AMDGPU][True16][CodeGen] Implement sgpr folding in true16 (#128929)Brox Chen
2025-03-28[AMDGPU] Unused sdst writing to null (#133229)Ana Mihajlovic
2025-03-26[AMDGPU][True16][CodeGen] srl pattern for true16 mode (#132987)Brox Chen
2025-03-18AMDGPU: Move insertion into V2SCopies map (#130776)Matt Arsenault
2025-03-13Reland "[AMDGPU] Remove s_delay_alu for VALU->SGPR->SALU (#127212)" (#131111)Ana Mihajlovic
2025-03-12[AMDGPU][True16] added Pre-RA hint to improve copy elimination (#103366)Brox Chen
2025-03-12Revert "[AMDGPU] Remove s_delay_alu for VALU->SGPR->SALU (#127212)"Kazu Hirata
2025-03-12[AMDGPU] Remove s_delay_alu for VALU->SGPR->SALU (#127212)Ana Mihajlovic
2025-03-08[AMDGPU] Change SGPR layout to striped caller/callee saved (#127353)Shilei Tian
2025-02-25[SelectionDAG] Utilizing target hook convertSelectOfConstantsToMath for Selec...Vikash Gupta
2025-02-21[AMDGPU][True16][CodeGen] flat/global/scratch load/store pseudo for true16 (#...Brox Chen
2025-02-21[AMDGPU][True16][CodeGen] build_vector pattern in true16 (#118904)Brox Chen
2025-01-24[AMDGPU] Restore SP from saved-FP or saved-BP (#124007)Aaditya
2025-01-23[AMDGPU] Occupancy w.r.t. workgroup size range is also a range (#123748)Lucas Ramirez
2025-01-16[AMDGPU][True16][MC][CodeGen] true16 for v_cndmask_b16 (#119736)Brox Chen
2024-12-09[CodeGen] [AMDGPU] Attempt DAGCombine for fmul with select to ldexp (#111109)Vikash Gupta
2024-11-08Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#...Shilei Tian
2024-11-08Revert "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#1...Shilei Tian
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