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path: root/llvm/test/CodeGen/AMDGPU/atomic_optimizations_raw_buffer.ll
AgeCommit message (Expand)Author
2025-10-22[AMDGPU] Reland "Remove redundant s_cmp_lg_* sX, 0" (#164201)LU-JOHN
2025-10-18Revert "[AMDGPU] Remove redundant s_cmp_lg_* sX, 0 " (#164116)Jan Patrick Lehr
2025-10-18[AMDGPU] Remove redundant s_cmp_lg_* sX, 0 (#162352)LU-JOHN
2025-07-23[RFC][NFC][AMDGPU] Remove `-verify-machineinstrs` from `llvm/test/CodeGen/AMD...Shilei Tian
2025-06-27[AMDGPU] Fix bad removal of s_delay_alu (#145728)Ana Mihajlovic
2025-03-13Reland "[AMDGPU] Remove s_delay_alu for VALU->SGPR->SALU (#127212)" (#131111)Ana Mihajlovic
2025-03-12Revert "[AMDGPU] Remove s_delay_alu for VALU->SGPR->SALU (#127212)"Kazu Hirata
2025-03-12[AMDGPU] Remove s_delay_alu for VALU->SGPR->SALU (#127212)Ana Mihajlovic
2025-01-30[AMDGPU] Rewrite GFX12 SGPR hazard handling to dedicated pass (#118750)Carl Ritson
2024-11-08Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#...Shilei Tian
2024-11-08Revert "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#1...Shilei Tian
2024-11-08[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)Shilei Tian
2024-10-21[AMDGPU] Skip VGPR deallocation for waveslot limited kernels (#112765)Stanislav Mekhanoshin
2024-09-04[AMDGPU] Mitigate GFX12 VALU read SGPR hazard (#100067)Carl Ritson
2024-07-26[AMDGPU] Remove -wavefrontsize32 and -wavefrontsize64 from GFX10+ tests (NFC)...Changpeng Fang
2024-07-23[AMDGPU] Codegen support for constrained multi-dword sloads (#96163)Christudasan Devadasan
2024-07-15[AMDGPU] Enable atomic optimizer for divergent i64 and double values (#96934)Vikram Hegde
2024-07-15Reapply "AMDGPU: Move attributor into optimization pipeline (#83131)" and fol...Matt Arsenault
2024-07-14Revert "AMDGPU: Move attributor into optimization pipeline (#83131)" and foll...dyung
2024-07-14AMDGPU: Move attributor into optimization pipeline (#83131)Matt Arsenault
2024-01-18[AMDGPU] CodeGen for GFX12 S_WAIT_* instructions (#77438)Jay Foad
2024-01-17[AMDGPU] Disable V_MAD_U64_U32/V_MAD_I64_I32 workaround for GFX12 (#77927)Jay Foad
2024-01-16[AMDGPU,test] Change llc -march= to -mtriple= (#75982)Fangrui Song
2023-12-25[LLVM] Make use of s_flbit_i32_b64 and s_ff1_i32_b64 (#75158)Acim Maravic
2023-12-15[AMDGPU] CodeGen for GFX12 VBUFFER instructions (#75492)Mirko Brkušanin
2023-10-09Revert "[CodeGen] Really renumber slot indexes before register allocation (#6...Jay Foad
2023-10-09[CodeGen] Really renumber slot indexes before register allocation (#67038)Jay Foad
2023-07-19[AMDGPU] Insert s_nop before s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)Jay Foad
2023-06-30Revert "[AMDGPU] Mark mbcnt as convergent"Sameer Sahasrabuddhe
2023-06-22[AMDGPU] Switch to the new cl option amdgpu-atomic-optimizer-strategy.Pravin Jagtap
2023-06-09[AMDGPU] Iterative scan implementation for atomic optimizer.Pravin Jagtap
2023-06-05[AMDGPU] Add buffer intrinsics that take resources as pointersKrzysztof Drewniak
2022-12-19[AMDGPU] Convert some tests to opaque pointers (NFC)Nikita Popov
2022-11-14[MachineCSE] Allow CSE for instructions with ignorable operandsGuozhi Wei
2022-10-06[Sink] Allow sinking of invariant loads across critical edgesCarl Ritson
2022-07-08[AMDGPU] Add GFX11 test coverageJay Foad
2022-06-16[AMDGPU] Change use null for dead sdst to be gfx1030+David Stuttard
2022-06-13[AMDGPU] Use null for dead sdst operandStanislav Mekhanoshin
2022-06-09[AMDGPU] Use v_mad_u64_u32 for IMAD32Stanislav Mekhanoshin
2022-03-29[AMDGPU] Generate checks in atomic_optimizations_*.llJay Foad
2022-02-18[CodeGen] Remove unneeded regex escaping in FileCheck patterns. NFC.Jay Foad
2021-03-19[AMDGPU] Remove weird target triples from tests. NFC.Jay Foad
2021-02-23[AMDGPU][SelectionDAG] Don't combine uniform multiplies to MUL_[UI]24Nicolai Hähnle
2020-10-27[AMDGPU] Move WQM Pass after MI SchedulerCarl Ritson
2020-03-31[AMDGPU] New llvm.amdgcn.ballot intrinsicSebastian Neubauer
2019-08-23[AMDGPU] gfx10 atomic optimizer changes.Jay Foad
2019-07-12[AMDGPU] Fix DPP combiner check for exec modificationJay Foad
2019-04-01[AMDGPU] Pre-allocate WWM registers to reduce VGPR pressure.Neil Henning
2019-03-05[AMDGPU] Fix DPP operand order in atomic optimizerCarl Ritson
2019-02-11[AMDGPU] Fix DPP sequence in atomic optimizer.Neil Henning
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