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path: root/llvm/test/CodeGen/AMDGPU/atomic_optimizations_local_pointer.ll
AgeCommit message (Expand)Author
2025-11-23Revert "[RegAlloc] Fix the terminal rule check for interfere with DstReg (#16...Aiden Grossman
2025-11-23[RegAlloc] Fix the terminal rule check for interfere with DstReg (#168661)hstk30-hw
2025-11-14AMDGPU: Select vector reg class for divergent build_vector (#168169)Matt Arsenault
2025-11-14AMDGPU: Use v_mov_b32 to implement divergent zext i32->i64 (#168166)Matt Arsenault
2025-11-11AMDGPU: Relax shouldCoalesce to allow more register tuple widening (#166475)Matt Arsenault
2025-10-28[AMDGPU] Rework GFX11 VALU Mask Write Hazard (#138663)Carl Ritson
2025-10-22[AMDGPU] Reland "Remove redundant s_cmp_lg_* sX, 0" (#164201)LU-JOHN
2025-10-18Revert "[AMDGPU] Remove redundant s_cmp_lg_* sX, 0 " (#164116)Jan Patrick Lehr
2025-10-18[AMDGPU] Remove redundant s_cmp_lg_* sX, 0 (#162352)LU-JOHN
2025-09-06AMDGPU: Allow folding multiple uses of some immediates into copies (#154757)Matt Arsenault
2025-06-27[AMDGPU] Fix bad removal of s_delay_alu (#145728)Ana Mihajlovic
2025-05-28MachineScheduler: Reset next cluster candidate for each node (#139513)Ruiling, Song
2025-05-16[MachineCopyPropagation] Make use of lane mask info in basic block liveins (#...Jay Foad
2025-03-28[AMDGPU] Unused sdst writing to null (#133229)Ana Mihajlovic
2025-03-13Reland "[AMDGPU] Remove s_delay_alu for VALU->SGPR->SALU (#127212)" (#131111)Ana Mihajlovic
2025-03-13AMDGPU: Replace undef global initializers in tests with poison (#131051)Matt Arsenault
2025-03-12Revert "[AMDGPU] Remove s_delay_alu for VALU->SGPR->SALU (#127212)"Kazu Hirata
2025-03-12[AMDGPU] Remove s_delay_alu for VALU->SGPR->SALU (#127212)Ana Mihajlovic
2025-02-01[MachineScheduler] Fix physreg dependencies of ExitSU (#123541)Sergei Barannikov
2025-01-30PeepholeOpt: Do not add subregister indexes to reg_sequence operands (#124111)Matt Arsenault
2024-11-26AMDGPU: Remove some -verify-machineinstrs from tests (#117736)Matt Arsenault
2024-11-08Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#...Shilei Tian
2024-11-08Revert "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#1...Shilei Tian
2024-11-08[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)Shilei Tian
2024-11-05[AMDGPU] Extend type support for update_dpp intrinsic (#114597)Stanislav Mekhanoshin
2024-10-21[AMDGPU] Skip VGPR deallocation for waveslot limited kernels (#112765)Stanislav Mekhanoshin
2024-09-23AMDGPU: Fix implicit vcc def to vcc_lo on wave32 targets (#109514)Matt Arsenault
2024-09-11[AMDGPU] Simplify and improve codegen for llvm.amdgcn.set.inactive (#107889)Jay Foad
2024-09-05[AMDGPU] V_SET_INACTIVE optimizations (#98864)Carl Ritson
2024-09-04[AMDGPU] Improve codegen for GFX10+ DPP reductions and scans (#107108)Jay Foad
2024-07-26[AMDGPU] Remove -wavefrontsize32 and -wavefrontsize64 from GFX10+ tests (NFC)...Changpeng Fang
2024-07-23[AMDGPU] Codegen support for constrained multi-dword sloads (#96163)Christudasan Devadasan
2024-07-15[AMDGPU] Enable atomic optimizer for divergent i64 and double values (#96934)Vikram Hegde
2024-07-15Reapply "AMDGPU: Move attributor into optimization pipeline (#83131)" and fol...Matt Arsenault
2024-07-14Revert "AMDGPU: Move attributor into optimization pipeline (#83131)" and foll...dyung
2024-07-14AMDGPU: Move attributor into optimization pipeline (#83131)Matt Arsenault
2024-07-08[AMDGPU] Cleanup bitcast spam in atomic optimizer (#96933)Vikram Hegde
2024-04-04[AMDGPU] Combine or remove redundant waitcnts at the end of each MBB (#87539)Jay Foad
2024-01-16[AMDGPU,test] Change llc -march= to -mtriple= (#75982)Fangrui Song
2023-12-25[LLVM] Make use of s_flbit_i32_b64 and s_ff1_i32_b64 (#75158)Acim Maravic
2023-12-15[AMDGPU][SIInsertWaitcnts] Do not add s_waitcnt when the counters are known t...Pierre van Houtryve
2023-10-30[AMDGPU] Select 64-bit imm moves if can be encoded as 32 bit operand (#70395)Stanislav Mekhanoshin
2023-08-30[AMDGPU] Support FAdd/FSub global atomics in AMDGPUAtomicOptimizer.Pravin Jagtap
2023-07-19[AMDGPU] Insert s_nop before s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)Jay Foad
2023-06-30Revert "[AMDGPU] Mark mbcnt as convergent"Sameer Sahasrabuddhe
2023-06-22[AMDGPU] Switch to the new cl option amdgpu-atomic-optimizer-strategy.Pravin Jagtap
2023-06-09[AMDGPU] Iterative scan implementation for atomic optimizer.Pravin Jagtap
2022-12-19[AMDGPU] Convert some tests to opaque pointers (NFC)Nikita Popov
2022-11-14[MachineCSE] Allow CSE for instructions with ignorable operandsGuozhi Wei
2022-10-06[Sink] Allow sinking of invariant loads across critical edgesCarl Ritson
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