summaryrefslogtreecommitdiff
path: root/llvm/test/CodeGen/AMDGPU/atomic_optimizations_global_pointer.ll
AgeCommit message (Expand)Author
2025-11-23Revert "[RegAlloc] Fix the terminal rule check for interfere with DstReg (#16...Aiden Grossman
2025-11-23[RegAlloc] Fix the terminal rule check for interfere with DstReg (#168661)hstk30-hw
2025-11-14AMDGPU: Use v_mov_b32 to implement divergent zext i32->i64 (#168166)Matt Arsenault
2025-11-11AMDGPU: Relax shouldCoalesce to allow more register tuple widening (#166475)Matt Arsenault
2025-10-28[AMDGPU] Rework GFX11 VALU Mask Write Hazard (#138663)Carl Ritson
2025-10-22[AMDGPU] Reland "Remove redundant s_cmp_lg_* sX, 0" (#164201)LU-JOHN
2025-10-18Revert "[AMDGPU] Remove redundant s_cmp_lg_* sX, 0 " (#164116)Jan Patrick Lehr
2025-10-18[AMDGPU] Remove redundant s_cmp_lg_* sX, 0 (#162352)LU-JOHN
2025-10-02PeepholeOpt: Fix losing subregister indexes on full copies (#161310)Matt Arsenault
2025-09-04[AMDGPU][True16][Codegen] remove another build_vector pattern from true16 (#1...Brox Chen
2025-08-22AMDGPU: Start considering new atomicrmw metadata on integer operations (#122138)Matt Arsenault
2025-08-22AMDGPU: Expand remaining system atomic operations (#122137)Matt Arsenault
2025-08-20[AMDGPU][True16][CodeGen] use vgpr16 for zext patterns (reopen #153894) (#154...Brox Chen
2025-08-18Revert "[AMDGPU][True16][CodeGen] use vgpr16 for zext patterns (#1538… (#15...Brox Chen
2025-08-18[AMDGPU][True16][CodeGen] use vgpr16 for zext patterns (#153894)Brox Chen
2025-07-23[RFC][NFC][AMDGPU] Remove `-verify-machineinstrs` from `llvm/test/CodeGen/AMD...Shilei Tian
2025-07-09[AMDGPU][True16][CodeGen] stop emitting spgr_lo16 from isel (#144819)Brox Chen
2025-07-03[PHIElimination] Revert #131837 #146320 #146337 (#146850)Guy David
2025-06-29[PHIElimination] Reuse existing COPY in predecessor basic block (#131837)Guy David
2025-06-27[AMDGPU] Fix bad removal of s_delay_alu (#145728)Ana Mihajlovic
2025-04-23[AMDGPU][True16][CodeGen] update GFX11Plus codegen test with true16 flag (#13...Brox Chen
2025-04-22Reland [SelectionDAG] Folding ZERO-EXTEND/SIGN_EXTEND poison to Poison value ...zhijian lin
2025-04-21Revert "[SelectionDAG] Folding ZERO-EXTEND/SIGN_EXTEND poison to Poison valu...Nico Weber
2025-04-21[SelectionDAG] Folding ZERO-EXTEND/SIGN_EXTEND poison to Poison value in get...zhijian lin
2025-04-17Re apply 130577 narrow math for and operand (#133896)Shoreshen
2025-04-01Revert "[AMDGPU][CodeGenPrepare] Narrow 64 bit math to 32 bit if profitable" ...Shoreshen
2025-04-01[AMDGPU][CodeGenPrepare] Narrow 64 bit math to 32 bit if profitable (#130577)Shoreshen
2025-03-28[AMDGPU] Unused sdst writing to null (#133229)Ana Mihajlovic
2025-03-13Reland "[AMDGPU] Remove s_delay_alu for VALU->SGPR->SALU (#127212)" (#131111)Ana Mihajlovic
2025-03-12Revert "[AMDGPU] Remove s_delay_alu for VALU->SGPR->SALU (#127212)"Kazu Hirata
2025-03-12[AMDGPU] Remove s_delay_alu for VALU->SGPR->SALU (#127212)Ana Mihajlovic
2025-02-24AMDGPU: Fix creating illegally typed readfirstlane in atomic optimizer (#128388)Matt Arsenault
2025-02-22PeepholeOpt: Allow introducing subregister uses on reg_sequence (#127052)Matt Arsenault
2025-02-01[MachineScheduler] Fix physreg dependencies of ExitSU (#123541)Sergei Barannikov
2025-01-30PeepholeOpt: Do not add subregister indexes to reg_sequence operands (#124111)Matt Arsenault
2025-01-30[AMDGPU] Rewrite GFX12 SGPR hazard handling to dedicated pass (#118750)Carl Ritson
2024-11-08Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#...Shilei Tian
2024-11-08Revert "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#1...Shilei Tian
2024-11-08[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)Shilei Tian
2024-11-05[AMDGPU] Extend type support for update_dpp intrinsic (#114597)Stanislav Mekhanoshin
2024-10-21[AMDGPU] Skip VGPR deallocation for waveslot limited kernels (#112765)Stanislav Mekhanoshin
2024-10-07[AMDGPU] Only emit SCOPE_SYS global_wb (#110636)Pierre van Houtryve
2024-09-23AMDGPU: Fix implicit vcc def to vcc_lo on wave32 targets (#109514)Matt Arsenault
2024-09-11[AMDGPU] Simplify and improve codegen for llvm.amdgcn.set.inactive (#107889)Jay Foad
2024-09-05[AMDGPU] V_SET_INACTIVE optimizations (#98864)Carl Ritson
2024-09-04[AMDGPU] Fix test update after #107108Jay Foad
2024-09-04[AMDGPU] Improve codegen for GFX10+ DPP reductions and scans (#107108)Jay Foad
2024-09-04[AMDGPU] Mitigate GFX12 VALU read SGPR hazard (#100067)Carl Ritson
2024-07-26[AMDGPU] Remove -wavefrontsize32 and -wavefrontsize64 from GFX10+ tests (NFC)...Changpeng Fang
2024-07-23[AMDGPU] Codegen support for constrained multi-dword sloads (#96163)Christudasan Devadasan
generated by cgit v1.2.3 (git 2.25.1) at 2026-06-01 10:26:07 +0000