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path: root/llvm/lib/Target/X86/X86InstrInfo.cpp
AgeCommit message (Expand)Author
2025-11-11[X86][AVX512] rematerialize smaller predicate masks (#166178)Ahmed Nour
2025-11-10CodeGen: Remove TRI arguments from stack load/store hooks (#158240)Matt Arsenault
2025-11-10CodeGen: Remove TRI argument from reMaterialize (#158229)Matt Arsenault
2025-11-10CodeGen: Remove TRI argument from getRegClass (#158225)Matt Arsenault
2025-11-10CodeGen: Keep reference to TargetRegisterInfo in TargetInstrInfo (#158224)Matt Arsenault
2025-10-31[X86] Remove AMX-TRANSPOSE (#165556)Mikołaj Piróg
2025-10-17[X86] Use pseudo instructions to zero registers in `buildClearRegister` (#163...Abhishek Kaushik
2025-09-29[X86][MemFold] Allow masked load folding if masks are equal (#161074)Phoebe Wang
2025-09-25[llvm] Fix X86InstrInfo.cpp build after #160188Jan Svoboda
2025-09-23[CodeGen] Rename isReallyTriviallyReMaterializable [nfc]Philip Reames
2025-09-23[X86] Invalid fp16 comparison fix (#160304)azwolski
2025-09-12CodeGen: Remove MachineFunction argument from getRegClass (#158188)Matt Arsenault
2025-09-11[llvm-mca][x86] Ensure avxvnni tests actually test the avxvnni instructions (...Simon Pilgrim
2025-09-08CodeGen: Pass SubtargetInfo to TargetGenInstrInfo constructors (#157337)Matt Arsenault
2025-08-29Reland "[X86][APX] Remove redundant TEST*ri instructions" (#156002)Phoebe Wang
2025-08-29Revert "[X86][APX] Remove redundant TEST*ri instructions" (#155968)Vitaly Buka
2025-08-28[X86][APX] Remove redundant TEST*ri instructions (#155586)Phoebe Wang
2025-08-26[X86] Fix spill issue for fr16 (#155225)Luo, Yuanke
2025-08-04Revert "[X86][ARM][RISCV][XCore][M68K] Invert the low bit to get the inverse ...Craig Topper
2025-08-04[X86][ARM][RISCV][XCore][M68K] Invert the low bit to get the inverse predicat...AZero13
2025-06-13[X86] X86InstrInfo::commuteInstructionImpl - remove (V)BLENDPD/S commutation ...Simon Pilgrim
2025-06-10[X86] commuteInstructionImpl - assert that only MOVSDrr is being commuted to ...Simon Pilgrim
2025-05-20[x64][win] Add compiler support for x64 import call optimization (equivalent ...Daniel Paoliello
2025-05-12[X86][APX] Fix issues of suppressing APX for relocation (#139285)Feng Zou
2025-04-29[X86][APX] Suppress EGPR/NDD instructions for relocations (#136660)Feng Zou
2025-04-25Revert "[X86][APX] Support peephole optimization with CCMP instruction (#1299...Feng Zou
2025-04-19[X86][APX] Handle AND_NF instruction for compare peephole (#136233)Evgenii Kudriashov
2025-04-18[Analysis] Remove implicit LocationSize conversion from uint64_t (#133342)Philip Reames
2025-04-15[NFC] Fix destroy typo. (#135640)Connector Switch
2025-03-29[X86] Use MCRegister. NFCCraig Topper
2025-03-26[CodeGen] Provide a target independent default for optimizeLoadInst [NFC]Philip Reames
2025-03-22[X86] Prevent APX NDD compression when it creates a partial write (#132051)Daniel Zabawa
2025-03-20[TTI] Use TypeSize in isLoadFromStackSlot and isStoreToStackSlot [nfc] (#132244)Philip Reames
2025-03-15[X86] Use Register and MCRegister. NFCCraig Topper
2025-03-15[CodeGen][X86] Use Register in TTI unfoldMemoryOperand interface. NFCCraig Topper
2025-03-15[X86][APX] Remove the EFLAGS def operand rather than the last one (#131430)Phoebe Wang
2025-03-13[MachineCombiner][Targets] Use Register in TII genAlternativeCodeSequence int...Craig Topper
2025-03-13[X86][APX] Add NF instructions to convertToThreeAddress functions (#130969)Phoebe Wang
2025-03-12[X86][NF] Switch the order of Inst and &Target.getInstruction(NewRec) (#130739)Phoebe Wang
2025-03-12[X86][APX] Support peephole optimization with CCMP instruction (#129994)Feng Zou
2025-03-10[X86][APX] Try to replace non-NF with NF instructions when optimizeCompareIns...Phoebe Wang
2025-02-24[CodeGen] Change copyPhysReg interface to use Register instead of MCRegister....Craig Topper
2025-02-19X86: Fix convertToThreeAddress losing subregister indexes (#124098)Matt Arsenault
2025-01-29[X86] Use new Flags argument to storeRegToStackSlot to simplify code. NFC (#1...Craig Topper
2025-01-23[X86] Handle BSF/BSR "zero-input pass through" behaviour (#123623)Simon Pilgrim
2025-01-22[llvm] Pass MachineInstr flags to storeRegToStackSlot/loadRegFromStackSlot (N...Venkata Ramanaiah Nalamothu
2025-01-02[X86][NFC] Move "_Int" after "k"/"kz" (#121450)Phoebe Wang
2024-11-22[X86] Add missing reg/imm attributes to VRNDSCALES instruction names (#117203)Simon Pilgrim
2024-11-21Revert "[X86] Recognize POP/ADD/SUB modifying rsp in getSPAdjust. (#114265) (...Phoebe Wang
2024-11-20[X86] Rename AVX512 VEXTRACT/INSERT??x? to VEXTRACT/INSERT??X? (#116826)Simon Pilgrim
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