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path: root/llvm/lib/Target/SystemZ/SystemZRegisterInfo.td
AgeCommit message (Expand)Author
2025-04-16[SystemZ] Add support for 16-bit floating point. (#109164)Jonas Paulsson
2023-12-15[SystemZ] Support i128 as legal type in VRs (#74625)Ulrich Weigand
2023-03-21[SystemZ] Fix modelling of composed subreg indices.Carl Ritson
2021-02-19[SystemZ/z/OS] Add XPLINK 64-bit calling convention to tablegen.Yusra Syeda
2020-04-25[TableGen] Drop deprecated leading # operation (NOP) and replace ## with #Fangrui Song
2019-05-13[SystemZ] Model floating-point control registerUlrich Weigand
2019-01-19Update the file headers across all of the LLVM projects in the monorepoChandler Carruth
2018-08-15[SystemZ] Replace subreg_r with subreg_hKrzysztof Parzyszek
2018-04-30[SystemZ] Do not use glue to represent condition code dependenciesUlrich Weigand
2018-03-16[SystemZ] Make AnyRegBitRegClass unallocatable.Jonas Paulsson
2018-03-02[SystemZ] Support vector registers in inline asmUlrich Weigand
2017-09-12[SystemZ] Add the CoveredBySubRegs bit to GPR64, GPR128 and FPR128 registers.Jonas Paulsson
2017-07-17[SystemZ] Add support for IBM z14 processor (3/3)Ulrich Weigand
2017-07-17[SystemZ] Add support for IBM z14 processor (2/3)Ulrich Weigand
2017-06-30[SystemZ] Add all remaining instructionsUlrich Weigand
2016-11-08[SystemZ] Model access registers as LLVM registersUlrich Weigand
2016-08-08[SystemZ] Add support for the .insn directiveZhan Jun Liau
2015-10-29[SystemZ] Make the CCRegs regclass non-allocatable.Jonas Paulsson
2015-05-05[SystemZ] Add z13 vector facility and MC supportUlrich Weigand
2015-05-04[SystemZ] Reclassify f32 subregs of f64 registersUlrich Weigand
2014-07-10[SystemZ] Fix FPR dwarf numberingRichard Sandiford
2013-10-01[SystemZ] Use upper words of GR64s for codegenRichard Sandiford
2013-09-30[SystemZ] Add GRH32 for the high word of a GR64Richard Sandiford
2013-09-30[SystemZ] Rename subregs and add subreg_h32Richard Sandiford
2013-09-30[SystemZ] Add change missing from previous commitRichard Sandiford
2013-09-30[SystemZ] Rename 32-bit GPR registersRichard Sandiford
2013-07-12[SystemZ] Fix parsing of inline asm registersRichard Sandiford
2013-05-31Make SubRegIndex size mandatory, following r183020.Ahmed Bougacha
2013-05-31Add a way to define the bit range covered by a SubRegIndex.Ahmed Bougacha
2013-05-22[SystemZ] Rename PSW to CCRichard Sandiford
2013-05-06[SystemZ] Add back endUlrich Weigand
2011-10-24Remove the SystemZ backend.Dan Gohman
2011-06-17Allocate SystemZ callee-saved registers backwards: R13-R6Jakob Stoklund Olesen
2011-06-15Use set operations instead of plain lists to enumerate register classes.Jakob Stoklund Olesen
2011-06-15Remove custom allocation orders in SystemZ.Jakob Stoklund Olesen
2011-05-30Remove the DwarfNumbers from the subregisters. They should use DW_OP_bit_pieceRafael Espindola
2011-01-10Rename TargetFrameInfo into TargetFrameLowering. Also, put couple of FIXMEs a...Anton Korobeynikov
2010-11-18Move hasFP() and few related hooks to TargetFrameInfo.Anton Korobeynikov
2010-05-28Merge the SystemZ subreg_even32 SubRegIndex into subreg_32bit. The SubRegIndicesJakob Stoklund Olesen
2010-05-26Replace the SubRegSet tablegen class with a less error-prone mechanism.Jakob Stoklund Olesen
2010-05-26Revert "Replace the SubRegSet tablegen class with a less error-prone mechanism."Jakob Stoklund Olesen
2010-05-26Replace the SubRegSet tablegen class with a less error-prone mechanism.Jakob Stoklund Olesen
2010-05-25Remove NumberHack entirely.Jakob Stoklund Olesen
2010-05-24Switch SubRegSet to using symbolic SubRegIndicesJakob Stoklund Olesen
2010-05-24Replace the tablegen RegisterClass field SubRegClassList with an alist-like dataJakob Stoklund Olesen
2010-05-24Use SubRegIndex in SystemZ.Jakob Stoklund Olesen
2009-07-16Out GR128 regclass is not a 'real' i128 one.Anton Korobeynikov
2009-07-16Add FP regsAnton Korobeynikov
2009-07-16Provide consistent subreg idx scheme. This (hopefully) fixes remaining divide...Anton Korobeynikov
2009-07-16Properly handle divides. As a bonus - implement memory versions of them.Anton Korobeynikov
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