summaryrefslogtreecommitdiff
path: root/llvm/lib/Target/SPIRV/SPIRVPreLegalizer.cpp
AgeCommit message (Expand)Author
2025-11-19[llvm] Use llvm::size (NFC) (#168675)Kazu Hirata
2025-10-31[SPIRV] Expand spv_bitcast intrinsic during instruction selection (#164884)Steven Perron
2025-09-30[SPIR-V] Implement SPV_KHR_float_controls2 (#146941)Marcos Maronas
2025-08-12[SPIRV] Create a new OpSelect selector and fix register types. (#152311)Farzon Lotfi
2025-08-06[SPIRV] Fix code quality issues. (#152005)Marcos Maronas
2025-05-26[SPIRV] Remove unused includes (NFC) (#141450)Kazu Hirata
2025-05-26Reland [SPIR-V] Support `SPV_INTEL_int4` extension (#141279)Viktoria Maximova
2025-05-23Revert "[SPIR-V] Support `SPV_INTEL_int4` extension" (#141219)Dmitry Sidorov
2025-05-22[SPIR-V] Support `SPV_INTEL_int4` extension (#141031)Viktoria Maximova
2025-05-14[GlobalISel] Add a GISelValueTracker printing pass (#139687)David Green
2025-04-10[SPIRV][NFC] Refactor pointer creation in GlobalRegistery (#134429)Steven Perron
2025-04-03[NFC] Cleanup pass initialization for SPIRV passes (#134189)Rahul Joshi
2025-03-29[GlobalISel][NFC] Rename GISelKnownBits to GISelValueTracking (#133466)Tim Gymnich
2025-03-26[SPIR-V] Rework duplicate tracker and tracking of IR entities and types to im...Vyacheslav Levytskyy
2025-03-14[SPIR-V] Support SPV_INTEL_fp_max_error extension for `!fpmath` metadata (#13...Viktoria Maximova
2025-03-08[SPIRV] Avoid repeated hash lookups (NFC) (#130391)Kazu Hirata
2025-03-06[SPIR-V] Add SPV_INTEL_memory_access_aliasing extension (#129800)Dmitry Sidorov
2025-02-25[SPIR-V] Fix generation of gMIR vs. SPIR-V code from utility methods (#128159)Vyacheslav Levytskyy
2025-02-10[NFC][LLVM] Remove unused `TargetIntrinsicInfo` class (#126003)Rahul Joshi
2025-01-17[SPIRV] add pre legalization instruction combine (#122839)Farzon Lotfi
2025-01-07[SPIR-V] Overhaul module analysis to improve translation speed and simplify t...Vyacheslav Levytskyy
2024-12-16[SPIR-V] Add saturation and float rounding mode decorations, a subset of arit...Vyacheslav Levytskyy
2024-12-09[SPIR-V] Improve general validity of emitted code between passes (#119202)Vyacheslav Levytskyy
2024-11-05[SPIR-V] No OpBitcast is generated for a bitcast between identical types (#11...Vyacheslav Levytskyy
2024-11-04[SPIR-V] Fix OpDecorate emission after vreg def. (#114426)Nathan Gauër
2024-10-30[SPIR-V] Do instruction selection for G_BITCAST on an earlier stage (#114216)Vyacheslav Levytskyy
2024-10-01[SPIR-V] Implement OpSpecConstantOp with ptr-cast operation (#109979)Vyacheslav Levytskyy
2024-10-01[SPIR-V] Fix inconsistency between previously deduced element type of a point...Vyacheslav Levytskyy
2024-09-26[SPIR-V] Allow intrinsics with aggregate return type to reach GlobalISel (#10...Vyacheslav Levytskyy
2024-09-24[SPIR-V] Fix bad insertion for type/id MIR (#109686)Nathan Gauër
2024-09-20[SPIR-V] Add SPIR-V structurizer (#107408)Nathan Gauër
2024-09-03[SPIR-V] Improve correctness of emitted MIR between passes for branching inst...Vyacheslav Levytskyy
2024-08-22[SPIR-V] Rework usage of virtual registers' types and classes (#104104)Vyacheslav Levytskyy
2024-08-14[SPIR-V] Add implementation of the non-const G_BUILD_VECTOR and fix emission ...Vyacheslav Levytskyy
2024-08-12[SPIR-V] Rework usage of virtual registers' types and classes (#101732)Vyacheslav Levytskyy
2024-07-11[SPIRV] Improve type inference of operand presented by opaque pointers and ag...Vyacheslav Levytskyy
2024-06-26[SPIR-V] Improve pattern matching and tracking of constant integers (#96615)Vyacheslav Levytskyy
2024-06-13[SPIR-V] Ensure that cleaning of temporary constants doesn't purge tracked co...Vyacheslav Levytskyy
2024-06-11[SPIR-V] Validate and fix bit width of scalar registers (#95147)Vyacheslav Levytskyy
2024-06-07[SPIR-V] Improve type inference, addrspacecast and dependencies between SPIR-...Vyacheslav Levytskyy
2024-06-06[SPIR-V] Add validation to the test case with get_image_array_size/get_image_...Vyacheslav Levytskyy
2024-06-03[SPIR-V] Fix legalize info for G_BITREVERSE (#93699)Vyacheslav Levytskyy
2024-05-29[SPIR-V] Implement correct zeroinitializer for extension types in SPIR-V Back...Vyacheslav Levytskyy
2024-05-24[SPIR-V] Inline assembly support (#93164)Vyacheslav Levytskyy
2024-05-17[SPIR-V] Ensure that we don't have a dangling BlockAddress constants after in...Vyacheslav Levytskyy
2024-05-14[SPIR-V] Introduce support for 'spirv.Decorations' metadata node in SPIR-V Ba...Vyacheslav Levytskyy
2024-04-26[SPIRV] Improve builtins matching and type inference in SPIR-V Backend, fix...Vyacheslav Levytskyy
2024-04-24[SPIR-V] Fix pre-legalizer pass in SPIR-V Backend to support more gMIR opcode...Vyacheslav Levytskyy
2024-04-24Bit width of input/result types in OpSConvert/OpUConvert must not be the same...Vyacheslav Levytskyy
2024-04-17[SPIR-V] Account for zext in a llvm intrinsic call (#88903)Vyacheslav Levytskyy
generated by cgit v1.2.3 (git 2.25.1) at 2026-06-10 02:51:37 +0000