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path: root/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
AgeCommit message (Expand)Author
2025-11-10CodeGen: Remove TRI argument from getRegClass (#158225)Matt Arsenault
2025-09-12CodeGen: Remove MachineFunction argument from getRegClass (#158188)Matt Arsenault
2025-09-12CodeGen: Remove MachineFunction argument from getPointerRegClass (#158185)Matt Arsenault
2025-08-08[PowerPC] fix lowering of SPILL_CRBIT on pwr9 and pwr10 (#146424)Paul Murphy
2025-06-18[PowerPC] Add code to spill and restore DMRp registers (#142443)Lei Huang
2025-06-12[PowerPC][NFC] Update lowering STXVP to STXV in Oct word spilling (#143953)Lei Huang
2025-06-12Revert "[PowerPC][NFC] Update lowering STXVP to STXV in Oct word spil… (#14...Lei Huang
2025-06-12[PowerPC][NFC] Update lowering STXVP to STXV in Oct word spilling (#142220)Lei Huang
2025-06-02[PowerPC] Spill and restore DMR register (#141530)Lei Huang
2025-05-22[PowerPC][NFC] clean up if-else block in PPCRegisterInfo.cpp (#140084)Lei Huang
2025-04-04[PowerPC] Fix instruction name for dmr insert (#134301)Lei Huang
2025-04-03[PowerPC] Deprecate uses of ISD::ADDC/ISD::ADDE/ISD::SUBC/ISD::SUBE (#133155)zhijian lin
2025-02-19Revert "[PowerPC] Deprecate uses of ISD::ADDC/ISD::ADDE/ISD::SUBC/ISD::SUBE (...David Tenty
2025-02-13[PowerPC] Deprecate uses of ISD::ADDC/ISD::ADDE/ISD::SUBC/ISD::SUBE (#116984)zhijian lin
2025-01-18[CodeGen] Use Register/MCRegister::isPhysical. NFCCraig Topper
2024-12-12CodeGen: Eliminate dynamic relocations in the register superclass tables. (#1...Owen Anderson
2024-12-11Revert "CodeGen: Eliminate dynamic relocations in the register superclass tab...Owen Anderson
2024-12-11CodeGen: Eliminate dynamic relocations in the register superclass tables. (#1...Owen Anderson
2024-11-14[PowerPC] Remove unused includes (NFC) (#116163)Kazu Hirata
2024-11-04[PowerPC] Utilize getReservedRegs to find asm clobberable registers. (#107863)zhijian lin
2024-05-29[PowerPC] option `-msoft-float` should not block the PC-relative address inst...zhijian lin
2024-04-24[CodeGen] Make the parameter TRI required in some functions. (#85968)Xu Zhang
2024-01-26[NFC] Rename TargetInstrInfo::FoldImmediate to TargetInstrInfo::foldImmediate...Shengchen Kan
2023-01-13[CodeGen][Target] Remove uses of Register::isPhysicalRegister/isVirtualRegist...Craig Topper
2022-11-22[PowerPC] Add handling for WACC register spilling.Stefan Pintilie
2022-11-18PEI should be able to use backward walk in replaceFrameIndicesBackward.Alexander Timofeev
2022-10-13[PowerPC] Stash GPR to VSR if emergency spill slot is not reachableNemanja Ivanovic
2022-10-09[PowerPC] Add vector pair calling convention for AIXTing Wang
2022-10-04[PowerPC] Fix the register allocation hints for ACC registers.Stefan Pintilie
2022-09-03[llvm] Use range-based for loops (NFC)Kazu Hirata
2022-08-10[PowerPC] Don't use the S30 and S31 regs for the pic codeUmesh Kalappa
2022-06-20[PowerPC] Disable automatic generation of STXVPNemanja Ivanovic
2022-06-16[PowerPC] Fix LQ-STQ instructions to use correct offset and baseAhsan Saghir
2022-06-06[PowerPC] Support huge frame size for PPC64Kai Luo
2022-03-16[NFC][CodeGen] Rename some functions in MachineInstr.h and remove duplicated ...Shengchen Kan
2022-03-16Cleanup codegen includesserge-sans-paille
2022-03-15[PowerPC][P10] Add Vector pair calling conventionStefan Pintilie
2022-03-10Revert "Cleanup codegen includes"Nico Weber
2022-03-10Cleanup codegen includesserge-sans-paille
2022-01-24[PowerPC] Emit warning when SP is clobbered by asmQuinn Pham
2022-01-19[NFC] Use Register instead of unsignedJim Lin
2021-09-14[PowerPC] Exploit Prefixed Load/Stores using the refactored Load/Store Implem...Amy Kwan
2021-07-29[PowerPC] Fix issue where hint was providing the incorrect regsiter class.Stefan Pintilie
2021-07-20[PowerPC] Inefficient register allocation of ACC registers results in many co...Stefan Pintilie
2021-06-15[PowerPC] Fix spilling of paired VSX registersNemanja Ivanovic
2021-06-15[PowerPC] Export 16 byte load-store instructionsKai Luo
2021-06-11[PowerPC] Relax register superclasses for paired memopsQiu Chaofan
2021-05-13[PowerPC] Add ROP Protection to prologue and epilogueStefan Pintilie
2021-05-10[PowerPC] Spilling to registers does not require frame index scavengingStefan Pintilie
2021-05-03[AIX] Remove unused vector registers from allocation order in the default Alt...Zarko Todorovski
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