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path: root/llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp
AgeCommit message (Expand)Author
2025-11-19CodeGen: Add subtarget to TargetLoweringBase constructor (#168620)Matt Arsenault
2025-11-18[NVPTX] TableGen-erate SDNode descriptions (#168367)Sergei Barannikov
2025-11-08[llvm] Remove unused local variables (NFC) (#167185)Kazu Hirata
2025-11-06[CodeGen] Delete two ComputeValueVTs overloads (NFC) (#166758)Sergei Barannikov
2025-10-16[NVPTX] fix truncating/extending loads/stores for v2i32 (#163838)Artem Belevich
2025-10-12[llvm] Use [[fallthrough]] instead of LLVM_FALLTHROUGH (NFC) (#163086)Kazu Hirata
2025-10-09[NVPTX] properly expand operations that we do not support on v2i32 (#162391)Artem Belevich
2025-10-06[clang][NVPTX] Add intrinsics and builtins for CVT RS rounding mode (#160494)Srinivasa Ravi
2025-10-02[NVPTX] expand trunc/ext on v2i32 (#161715)Artem Belevich
2025-09-26[NVPTX] legalize v2i32 to improve compatibility with v2f32 (#153478)Princeton Ferro
2025-09-24[NVVM][NVPTX] Add support for tcgen05.mma (#151949)Pradeep Kumar
2025-09-22[NVPTX] Add 3-operand fmin/fmax DAGCombines (#159729)Lewis Crawford
2025-08-29[NVPTX] Add max/minimumnum to ISel (#155804)Lewis Crawford
2025-08-28[NVPTX] Support i256 load/store with 256-bit vector load (#155198)Alex MacLean
2025-08-28[NVPTX] add support for 128-bit atomics (#154852)Alex MacLean
2025-08-25Reland "[NVPTX] Legalize aext-load to zext-load to expose more DAG combines" ...Alex MacLean
2025-08-22Revert "[NVPTX] Legalize aext-load to zext-load to expose more DAG combines (...Joseph Huber
2025-08-21[NVPTX] Legalize aext-load to zext-load to expose more DAG combines (#154251)Alex MacLean
2025-08-21[NVPTX] Disable v2f32 registers when no operations supported, or via cl::opt ...Alex MacLean
2025-08-20[NVPTX] Implement computeKnownBitsForTargetNode for LoadV (#154165)Kevin McAfee
2025-08-17[llvm] Remove unused includes (NFC) (#154051)Kazu Hirata
2025-08-14[NVPTX] Remove `UnsafeFPMath` uses (#151479)paperchalice
2025-08-11[NVPTX] expand extractelt(v2f32) with dynamic index (#153078)Princeton Ferro
2025-08-07[NVPTX] Add prefetch tensormap variant (#146203)Abhilash Majumder
2025-08-06[NVPTX] lower VECREDUCE min/max to 3-input on sm_100+ (#136253)Princeton Ferro
2025-08-01[NVPTX] Vectorize loads when lowering of byval calls, misc. cleanup (#151070)Alex MacLean
2025-07-31[NVPTX] fix type propagation when expanding Store[V4 -> V8] (#151576)Princeton Ferro
2025-07-30[NVPTX] Enhance `mul.wide` and `mad.wide` peepholes (#150477)Justin Fargnoli
2025-07-28[NVPTX] Fix v2i8 call lowering, use generic ld/st nodes for call params (#146...Alex MacLean
2025-07-24[LLVM][NVPTX] Upstream tanh intrinsic for libdevice (#149596)Meredith Julian
2025-07-22[NVPTX] Add SimplifyDemandedBitsForTargetNode for PRMT (#149395)Alex MacLean
2025-07-22[NVPTX] Assert PRMT operands are of correct type (NFC) (#150104)Alex MacLean
2025-07-20[NVPTX] Lower stmatrix intrinsics to PTX (#148561)Pecco
2025-07-18[NVPTX] Prevent fptrunc of v2f32 from being folded into store (#149571)Alex MacLean
2025-07-18[NVPTX] don't erase CopyToRegs when folding movs into loads (#149393)Princeton Ferro
2025-07-17[NVPTX] Add PRMT constant folding and cleanup usage of PRMT node (#148906)Alex MacLean
2025-07-15[NVPTX] Add syncscope support for cmpxchg (#140812)Akshay Deodhar
2025-07-13[NVPTX] Use PRMT more widely, and improve folding around this instruction (#1...Alex MacLean
2025-07-11 [NVPTX] support f32x2 instructions for sm_100+ (#126337)Princeton Ferro
2025-07-01[NVPTX] Further cleanup call isel (#146411)Alex MacLean
2025-06-30[DAGCombiner] Remove `UnsafeFPMath` usage in `visitFSUBForFMACombine` etc. (#...paperchalice
2025-06-27[NVPTX] Fixup v2i8 parameter and return lowering (#145585)Alex MacLean
2025-06-25[NVPTX] Consolidate and cleanup various NVPTXISD nodes (NFC) (#145581)Alex MacLean
2025-06-24[NVPTX] fold movs into loads and stores (#144581)Princeton Ferro
2025-06-23[NVPTX] Rename register classes after float register removal (NFC) (#145255)Alex MacLean
2025-06-12[NVPTX] Consistently check fast-math flags when lowering fsqrt (#143776)Alex MacLean
2025-05-28Warn on misuse of DiagnosticInfo classes that hold Twines (#137397)Justin Bogner
2025-05-27[NVPTX] Add -nvptx-prec-divf32=3 to disable ftz for f32 fdiv (#141276)Alex MacLean
2025-05-25[NVPTX][NFC] Refactor and cleanup NVPTXISelLowering call lowering 2/n (#137666)Alex MacLean
2025-05-21[NVPTX] Remove Float register classes (#140487)Alex MacLean
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