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path: root/llvm/lib/Target/AVR/AVRExpandPseudoInsts.cpp
AgeCommit message (Expand)Author
2025-07-14[AVR] Simplify SPWRITE on XMEGA (#147210)Tom Vijlbrief
2025-04-07[NFC][LLVM] Cleanup pass initialization for ARM/ARV/Lanai/X86/XCore (#134400)Rahul Joshi
2023-06-11[AVR] Fix incorrect expansion of pseudo instruction ROLBRdBen Shi
2023-06-11[AVR] Enable sub register livenessBen Shi
2023-06-04[AVR] Fix incorrect operands of pseudo instruction 'ROLBRd'Patryk Wychowaniec
2023-04-17[AVR] Fix an issue of writing 16-bit portsBen Shi
2023-04-06[AVR] Fix incorrect expansion of pseudo instructions LPMWRdZ/ELPMWRdZBen Shi
2023-03-24[AVR] Do not emit 'LPM Rd, Z' on devices without FeatureLPMXBen Shi
2023-03-21[AVR] Fix incorrect expansion of the pseudo 'ELPMBRdZ' instructionBen Shi
2023-01-10[AVR] Do not select unimplemented pseudo instructionsBen Shi
2022-12-22[AVR] Do not emit instructions invalid for attiny10Ayke van Laethem
2022-11-28[AVR] Do not use R0/R1 on avrtinyAyke van Laethem
2022-11-27[AVR] Remove unused register scavengerAyke van Laethem
2022-08-15[AVR] Only push and clear R1 in interrupts when necessaryAyke van Laethem
2022-08-15[AVR] Use @earlyclobber instead of register scavengingAyke van Laethem
2022-05-06[AVR][NFC] Eliminate warning 'unused variable'Ben Shi
2022-05-05[AVR] Always expand STDSPQRr & STDWSPQRrPatryk Wychowaniec
2022-04-29AVRExpandPseudoInsts.cpp: Fix a warning. [-Wunused-but-set-variable]NAKAMURA Takumi
2022-04-11[AVR] Merge AVRRelaxMemOperations into AVRExpandPseudoInstsPatryk Wychowaniec
2022-03-26[AVR] Optimize int16 airthmetic right shift for shift amount 7/14/15Ben Shi
2022-03-25[AVR][NFC] Fix incorrect register states in expanding pseudo instructionsBen Shi
2022-02-02[AVR] Fix atomicrmw result valueAyke van Laethem
2022-01-20[AVR] Generate ELPM for loading byte/word from extended program memoryBen Shi
2022-01-04[AVR] Optimize int16 shift operation for shift amount greater than 8Ben Shi
2022-01-04Remove an unused variable, NFC.Haojian Wu
2022-01-04[AVR] Optimize int8 arithmetic right shift 6 bitsBen Shi
2022-01-04Revert "[AVR] Optimize int8 arithmetic right shift 6 bits"Ben Shi
2022-01-04[AVR] Optimize int8 arithmetic right shift 6 bitsBen Shi
2021-09-04[NFC] Run clang-format on llvm/lib/Trget/AVR/Shivam Gupta
2021-07-24[AVR] Fix rotate instructionsAyke van Laethem
2021-07-24[AVR] Improve 8/16 bit atomic operationsAyke van Laethem
2021-05-31[AVR][NFC] Refactor 8-bit & 16-bit shiftsBen Shi
2021-03-04[AVR] Fix lifeness issues in the AVR backendAyke van Laethem
2021-03-03[AVR] Fix def state of operandsAyke van Laethem
2021-03-03[AVR] Fix expansion of NEGWAyke van Laethem
2021-01-28[AVR] Optimize 16-bit int shiftBen Shi
2021-01-24[AVR] Optimize 8-bit int shiftBen Shi
2020-11-17[AVR] Optimize the 16-bit NEGW pseudo instructionBen Shi
2020-03-05[AVR][NFC] Use Register instead of unsignedJim Lin
2020-03-03[AVR] Fix incorrect register state for LDRdPtrJim Lin
2019-12-23[AVR] Fix codegen for rotate instructionsJim Lin
2019-08-15Apply llvm-prefer-register-over-unsigned from clang-tidy to LLVMDaniel Sanders
2019-08-03Finish moving TargetRegisterInfo::isVirtualRegister() and friends to llvm::Re...Sylvestre Ledru
2019-01-20[AVR] Fix codegen bug in 16-bit loadsDylan McKay
2019-01-20Revert "[AVR] Fix codegen bug in 16-bit loads"Dylan McKay
2019-01-19Update the file headers across all of the LLVM projects in the monorepoChandler Carruth
2019-01-18[AVR] Fix codegen bug in 16-bit loadsDylan McKay
2018-09-01[AVR] Redefine the 'LSL' instruction as an alias of 'ADD'Dylan McKay
2018-09-01[AVR] Define the ROL instruction as an alias of ADCDylan McKay
2018-08-16[MI] Change the array of `MachineMemOperand` pointers to beChandler Carruth
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