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path: root/llvm/lib/Target/ARM/ARMISelLowering.cpp
AgeCommit message (Expand)Author
2025-11-19CodeGen: Add subtarget to TargetLoweringBase constructor (#168620)Matt Arsenault
2025-11-18[ARM] TableGen-erate node descriptions (#168212)Sergei Barannikov
2025-11-12[ARM] Prevent stack argument overwrite during tail calls (#166492)David Tellenbach
2025-11-04DAG: Merge all sincos_stret emission code into legalizer (#166295)Matt Arsenault
2025-11-03Revert "ARM: Remove unnecessary manual ABI lowering for sincos_stret (#166040...Matt Arsenault
2025-11-03ARM: Remove unnecessary manual ABI lowering for sincos_stret (#166040)Matt Arsenault
2025-10-30[ARM] Mark function calls as possibly changing FPSCR (#160699)Erik Enikeev
2025-10-29[ARM] Add instruction selection for strict FP (#160696)Erik Enikeev
2025-10-28DAG: Consider __sincos_stret when deciding to form fsincos (#165169)Matt Arsenault
2025-10-24CodeGen: Remove overrides of getSSPStackGuardCheck (NFC) (#164044)Matt Arsenault
2025-10-23[ARM][KCFI] Add backend support for Kernel Control-Flow Integrity (#163698)Kees Cook
2025-10-21[Clang][LLVM] Support for Fuchsia on ARM (#163848)Petr Hosek
2025-10-21[ARM][SDAG] Add llvm.lround half promotion. (#164235)David Green
2025-10-17CodeGen: Fix hardcoded libcall names in insertSSPDeclarations (NFC) (#163710)Matt Arsenault
2025-10-11[ARM][TargetLowering] Combine Level should not be a factor in shouldFoldConst...AZero13
2025-10-10CodeGen: Remove unused IntrinsicLowering includes (#162844)Matt Arsenault
2025-10-07[ARM][SDAG] Half promote llvm.lrint nodes. (#161088)David Green
2025-09-26[ARM] Improve comment on the 'J' inline asm modifier. (#160712)Simon Tatham
2025-09-26[ARM] Remove `UnsafeFPMath` uses in code generation part (#160801)paperchalice
2025-09-25[TargetLowering][ExpandABD] Prefer selects over usubo if we do the same for u...AZero13
2025-09-19[ARM] Replace ABS and tABS machine nodes with custom lowering (#156717)AZero13
2025-09-11[ARM] Allow s constraints on half (#157860)Nikita Popov
2025-09-06[SelectionDAG][ARM] Propagate fast math flags in visitBRCOND (#156647)paperchalice
2025-09-05[DAG][ARM] canCreateUndefOrPoisonForTargetNode - ARMISD VORRIMM\VBICIMM nodes...woruyu
2025-09-04[DAG][ARM] ComputeKnownBitsForTargetNode - add handling for ARMISD VORRIMM\VB...woruyu
2025-09-04[CodeGen] Remove ExpandInlineAsm hook (#156617)Nikita Popov
2025-09-02[NFC] RuntimeLibcalls: Prefix the impls with 'Impl_' (#153850)Daniel Paoliello
2025-08-31[ARM] Simplify LowerCMP (NFC) (#156198)AZero13
2025-08-26[IA][RISCV] Recognize interleaving stores that could lower to strided segment...Min-Yih Hsu
2025-08-25[ARM] Set isCheapToSpeculateCtlz as true for hasV5TOps and no Thumb 1 (#154848)AZero13
2025-08-25[ARM] Remove an unnecessary cast (NFC) (#155206)Kazu Hirata
2025-08-23RuntimeLibcalls: Add entries for stackprotector globals (#154930)Matt Arsenault
2025-08-15[CodeGen] Give ArgListEntry a proper constructor (NFC) (#153817)Nikita Popov
2025-08-14ARM: Move half convert libcall config to tablegen (#153389)Matt Arsenault
2025-08-14ARM: Move more aeabi libcall config into tablegen (#152109)Matt Arsenault
2025-08-14ARM: Move calling conv config to RuntimeLibcalls (#152065)Matt Arsenault
2025-08-13[ARM] Protect against odd sized vectors in isVTRNMask and friends (#153413)David Green
2025-08-12[IA][RISCV] Recognize deinterleaved loads that could lower to strided segment...Min-Yih Hsu
2025-08-08[ARM] Have custom lowering for ucmp and scmp (#149315)AZero13
2025-08-06[Target] Remove unnecessary casts (NFC) (#152262)Kazu Hirata
2025-08-06[ARM] Fix inline asm register validation for vector types (#152175)eleviant
2025-08-06RuntimeLibcalls: Add entries for __security_check_cookie (#151843)Matt Arsenault
2025-08-06ARM: Remove redundant or buggy config of __aeabi_d2h (#152126)Matt Arsenault
2025-08-05ARM: Remove idiv runtime call aliases (#152098)Matt Arsenault
2025-08-01[SelectionDAG] Move sign pattern check from AArch64 and ARM to general Select...AZero13
2025-07-30[llvm] Extract and propagate callee_type metadataPrabhu Rajasekaran
2025-07-28[CodeGen] More consistently expand float ops by default (#150597)Nikita Popov
2025-07-24[ARM] Emit error message when incompatible reg is specified (#147559)eleviant
2025-07-22[IA] Support vp.store in lowerinterleavedStore (#149605)Philip Reames
2025-07-17[IA] Support vp.load in lowerInterleavedLoad [nfc-ish] (#149174)Philip Reames
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