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path: root/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
AgeCommit message (Expand)Author
2025-11-20[SDAG] Fix whitespace errors (NFC) (#168897)Ramkumar Ramachandra
2025-11-19DAG: Use poison for some vector result widening (#168290)Matt Arsenault
2025-11-19DAG: Use poison when splitting vector_shuffle results (#168176)Matt Arsenault
2025-11-15[SelectionDAG] Fix AArch64 machine verifier bug when expanding LOOP_DEPENDENC...AZero13
2025-11-15DAG: Use poison in SplitVecRes_VP_LOAD_FF (#167753)Matt Arsenault
2025-11-15DAG: Use poison when legalizing scalar_to_vector results (#167751)Matt Arsenault
2025-11-12DAG: Use poison when widening build_vector (#167631)Matt Arsenault
2025-11-07Add `llvm.vector.partial.reduce.fadd` intrinsic (#159776)Damian Heaton
2025-10-23[SelectionDAG] Legalize <1 x T> vector types for atomic load (#148894)jofrn
2025-10-08[LegalizeTypes] Use GetSplitVector in SplitVec(Res/Op)_PARTIAL_REDUCE_MLA (#1...Craig Topper
2025-10-02[LLVM][CodeGen][SVE] Remove failure cases when widening vector load/store ops...Paul Walker
2025-09-12[SelectionDAG] Use getShiftAmountConstant. (#158395)Craig Topper
2025-09-02[Intrinsics][AArch64] Add intrinsics for masking off aliasing vector lanes (#...Sam Tebbs
2025-08-27[CodeGen][RISCV] Add support of RISCV nontemporal to vector predication instr...daniel-trujillo-bsc
2025-08-21[SDAG[[X86] Added method to scalarize `STRICT_FSETCC` (#154486)Abhishek Kaushik
2025-08-21DAG: Handle half spanning extract_subvector in type legalization (#154101)Matt Arsenault
2025-08-20DAG: Avoid creating illegal extract_subvector in legalizer (#154100)Matt Arsenault
2025-08-05[VP][RISCV] Add a vp.load.ff intrinsic for fault only first load. (#128593)Craig Topper
2025-07-22[SelectionDAG] Pass SDNodeFlags through getNode instead of setFlags. (#149852)Craig Topper
2025-06-23[SelectionDAG][RISCV] Add support for splitting vp.splice (#145184)Craig Topper
2025-06-14[SelectionDAG] Take passthru into account when widening ISD::MLOAD (#144170)Min-Yih Hsu
2025-06-09[SDAG] Add partial_reduce_sumla node (#141267)Philip Reames
2025-06-06[AArch64][SDAG] Fix selection of extend of v1if16 SETCC (#140274)Benjamin Maxwell
2025-05-27[AArch64] Allow lowering of more types to GET_ACTIVE_LANE_MASK (#140062)Kerry McLaughlin
2025-05-22[SelectionDAG][RISCV] Use VP_STORE to widen MSTORE in type legalization when ...Craig Topper
2025-05-21[SelectionDAG] Simplify creation of getStoreVP in WidenVecOp_STORE. NFCCraig Topper
2025-05-21[SelectionDAG][RISCV] Use VP_LOAD to widen MLOAD in type legalization when po...Craig Topper
2025-05-16[SelectionDAG] Use getInsertSubvector/VectorElt and getExtractSubvector/Vecto...Craig Topper
2025-05-16[SelectionDAG] Rename MemSDNode::getOriginalAlign to getBaseAlign. NFC (#139930)Craig Topper
2025-05-15CodeGen: Add ISD::AssertNoFPClass (#138839)YunQiang Su
2025-05-13[LLVM][SelectionDAG] Simplify SplitVecOp_VSETCC. (#139295)Paul Walker
2025-05-01[SelectionDAG] Improve type legalisation for PARTIAL_REDUCE_MLA (#130935)Nicholas Guy
2025-04-30Revert "CodeGen: Add ISD::AssertNoFPClass (#135946)"YunQiang Su
2025-04-25CodeGen: Add ISD::AssertNoFPClass (#135946)YunQiang Su
2025-04-15[LegalizeTypes] Check getTypeAction before calling GetScalarizedVector. (#135...Craig Topper
2025-04-10Reland "[SelectionDAG] Introducing a new ISD::POISON SDNode to represent the ...zhijian lin
2025-04-09Revert "[SelectionDAG] Introducing a new ISD::POISON SDNode to represent the ...Jakub Kuderski
2025-04-07[SelectionDAG] Introducing a new ISD::POISON SDNode to represent the poison v...zhijian lin
2025-02-18[SelectionDAG] Add PARTIAL_REDUCE_U/SMLA ISD Nodes (#125207)James Chesterman
2025-02-12[AArch64][DAG] Allow fptos/ui.sat to scalarized. (#126799)David Green
2025-02-11[IR] Add llvm.sincospi intrinsic (#125873)Benjamin Maxwell
2025-02-07[IR] Add `llvm.modf` intrinsic (#121948)Benjamin Maxwell
2025-02-05[IR][RISCV] Add llvm.vector.(de)interleave3/5/7 (#124825)Min-Yih Hsu
2025-01-28[SelectionDAG] WidenVecOp_INSERT_SUBVECTOR - Replace `INSERT_SUBVECTOR` with ...abhishek-kaushik22
2025-01-13[RISCV][CG]Use processShuffleMasks for per-register shufflesAlexey Bataev
2025-01-11[DAG] Allow AssertZExt to scalarize. (#122463)David Green
2025-01-06[X86] Support lowering of FMINIMUMNUM/FMAXIMUMNUM (#121464)Phoebe Wang
2024-12-10[GISel][SDAG] Avoid push_back in loops for some shuffle mask handling. (#119434)Craig Topper
2024-11-21[SDAG] [X86] Extend SplitVecOp_VSETCC for STRICT_FSETCCS (#116768)abhishek-kaushik22
2024-10-31[SDAG] Simplify `SDNodeFlags` with bitwise logic (#114061)Yingwei Zheng
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