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path: root/llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h
AgeCommit message (Expand)Author
2025-10-31[SelectionDAG][RISCV] Support STACK/PATCHPOINT in SoftenFloatOperand. (#165922)Craig Topper
2025-10-23[SelectionDAG] Legalize <1 x T> vector types for atomic load (#148894)jofrn
2025-10-11Fix legalizing `FNEG` and `FABS` with `TypeSoftPromoteHalf` (#156343)beetrees
2025-10-07[ARM][SDAG] Half promote llvm.lrint nodes. (#161088)David Green
2025-09-02[Intrinsics][AArch64] Add intrinsics for masking off aliasing vector lanes (#...Sam Tebbs
2025-08-21[SDAG[[X86] Added method to scalarize `STRICT_FSETCC` (#154486)Abhishek Kaushik
2025-08-13[PowerPC][CodeGen] Expand ISD::AssertNoFPClass for ppc_fp128 (#152357)Amy Kwan
2025-08-05[VP][RISCV] Add a vp.load.ff intrinsic for fault only first load. (#128593)Craig Topper
2025-07-26DAG: Emit an error if trying to legalize read/write register with illegal typ...Matt Arsenault
2025-07-09DAG: Fall back to separate sin and cos when softening sincos (#147468)Matt Arsenault
2025-06-23[SelectionDAG][RISCV] Add support for splitting vp.splice (#145184)Craig Topper
2025-06-05[LegalizeTypes][MSP430] Soften FAKE_USE operand (#142714)Acthink Yang
2025-05-27[AArch64] Allow lowering of more types to GET_ACTIVE_LANE_MASK (#140062)Kerry McLaughlin
2025-05-15[SelectionDAG] Add an ISD node for for get.active.lane.mask (#139084)Kerry McLaughlin
2025-05-15CodeGen: Add ISD::AssertNoFPClass (#138839)YunQiang Su
2025-03-19DAG: Fix promote of half freeze (#131844)Matt Arsenault
2025-03-05[SDAG] Add missing SoftenFloatRes legalization for FMODF (#129264)Benjamin Maxwell
2025-02-25[SDAG] Add missing ppc_fp128 ExpandFloatRes for sincos[pi] (#128514)Benjamin Maxwell
2025-02-20[SDAG] Add missing ppc_fp128 ExpandFloatRes legalization for modf (#127895)Benjamin Maxwell
2025-02-18[SelectionDAG] Add PARTIAL_REDUCE_U/SMLA ISD Nodes (#125207)James Chesterman
2025-02-12[AArch64][DAG] Allow fptos/ui.sat to scalarized. (#126799)David Green
2025-01-20[SDAG] Add an ISD node to help lower vector.extract.last.active (#118810)Graham Hunter
2025-01-11[DAG] Allow AssertZExt to scalarize. (#122463)David Green
2024-12-09Reapply "[DAGCombiner] Add support for scalarising extracts of a vector setcc...David Sherwood
2024-11-20[SDAG] Generalize FSINCOS type legalization (NFC) (#116848)Benjamin Maxwell
2024-11-18[SelectionDAG] Support integer promotion for VP_LOAD and VP_STORE (#81299)Lei Huang
2024-11-09[LegalizeTypes] Support softening FMINIMUM/FMAXIMUM (#115463)Alex Bradbury
2024-10-29[IR] Add `llvm.sincos` intrinsic (#109825)Benjamin Maxwell
2024-10-16[X86][CodeGen] Add base atan2 intrinsic lowering (p4) (#110760)Tex Riddell
2024-09-13[x86] Add lowering for `@llvm.experimental.vector.compress` (#104904)Lawrence Benson
2024-08-30[AArch64][SelectionDAG] Vector splitting and promotion for histogram intrinsi...Max Beck-Jones
2024-08-29[ExtendLifetimes] Implement llvm.fake.use to extend variable lifetimes (#86149)Stephen Tozer
2024-08-21Scalarize the vector inputs to llvm.lround intrinsic by default. (#101054)Sumanth Gundapaneni
2024-08-15[LegalizeTypes][AMDGPU]: Allow for scalarization of insert_subvector (#104236)Jeffrey Byrnes
2024-08-15Intrinsic: introduce minimumnum and maximumnum for IR and SelectionDAG (#96649)YunQiang Su
2024-08-08[DAG] Add legalization handling for ABDS/ABDU (#92576) (REAPPLIED)Simon Pilgrim
2024-08-07Revert b1234ddbe2652aa7948242a57107ca7ab12fd2f8. "[DAG] Add legalization hand...Simon Pilgrim
2024-08-06[DAG] Add legalization handling for ABDS/ABDU (#92576)Simon Pilgrim
2024-07-17[LLVM] Add `llvm.experimental.vector.compress` intrinsic (#92289)Lawrence Benson
2024-07-17[VP][RISCV] Introduce vp.splat and RISC-V. (#98731)Yeting Kuo
2024-07-11[X86][CodeGen] Add base trig intrinsic lowerings (#96222)Farzon Lotfi
2024-07-11[Patchpoint] Implement integer result type legalization for patchpoints (#97278)Csanád Hajdú
2024-06-21Revert "Intrinsic: introduce minimumnum and maximumnum (#93841)"Nikita Popov
2024-06-21Intrinsic: introduce minimumnum and maximumnum (#93841)YunQiang Su
2024-06-17[SelectionDAG] Add support for the 3-way comparison intrinsics [US]CMP (#91871)Poseydon42
2024-06-12[DAG] Add legalization handling for AVGCEIL/AVGFLOOR nodes (#92096)Simon Pilgrim
2024-06-05[x86] Add tan intrinsic part 4 (#90503)Farzon Lotfi
2024-05-29[ValueTypes] Remove MVT::MAX_ALLOWED_VALUETYPE. NFC (#93654)Craig Topper
2024-05-28[LegalizeTypes] Use VP_AND and VP_SHL/VP_SRA to promote operands fo VP arithm...Craig Topper
2024-05-07AMDGPU: Don't bitcast float typed atomic store in IR (#90116)Matt Arsenault
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