[CodeGen] Rename RegisterMaskPair to VRegMaskOrUnit. NFC (#123799)

This holds a physical register unit or virtual register and mask.

While I was here I've used emplace_back and removed an unneeded use of a
template.

5 files changed, 76 insertions, 81 deletions

diff --git a/llvm/lib/CodeGen/MachinePipeliner.cpp b/llvm/lib/CodeGen/MachinePipeliner.cpp
index 54d9c1cf08e3..0d5dc9615900 100644
--- a/llvm/lib/CodeGen/MachinePipeliner.cpp
+++ b/llvm/lib/CodeGen/MachinePipeliner.cpp
@@ -1981,7 +1981,7 @@ static void computeLiveOuts(MachineFunction &MF, RegPressureTracker &RPTracker,
                             NodeSet &NS) {
   const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
   MachineRegisterInfo &MRI = MF.getRegInfo();
-  SmallVector<RegisterMaskPair, 8> LiveOutRegs;
+  SmallVector<VRegMaskOrUnit, 8> LiveOutRegs;
   SmallSet<unsigned, 4> Uses;
   for (SUnit *SU : NS) {
     const MachineInstr *MI = SU->getInstr();
@@ -2002,13 +2002,11 @@ static void computeLiveOuts(MachineFunction &MF, RegPressureTracker &RPTracker,
         Register Reg = MO.getReg();
         if (Reg.isVirtual()) {
           if (!Uses.count(Reg))
-            LiveOutRegs.push_back(RegisterMaskPair(Reg,
-                                                   LaneBitmask::getNone()));
+            LiveOutRegs.emplace_back(Reg, LaneBitmask::getNone());
         } else if (MRI.isAllocatable(Reg)) {
           for (MCRegUnit Unit : TRI->regunits(Reg.asMCReg()))
             if (!Uses.count(Unit))
-              LiveOutRegs.push_back(
-                  RegisterMaskPair(Unit, LaneBitmask::getNone()));
+              LiveOutRegs.emplace_back(Unit, LaneBitmask::getNone());
         }
       }
   RPTracker.addLiveRegs(LiveOutRegs);
diff --git a/llvm/lib/CodeGen/MachineScheduler.cpp b/llvm/lib/CodeGen/MachineScheduler.cpp
index 91aaeea156c4..393530f56cc2 100644
--- a/llvm/lib/CodeGen/MachineScheduler.cpp
+++ b/llvm/lib/CodeGen/MachineScheduler.cpp
@@ -1288,7 +1288,7 @@ void ScheduleDAGMILive::initRegPressure() {
 
   // Account for liveness generated by the region boundary.
   if (LiveRegionEnd != RegionEnd) {
-    SmallVector<RegisterMaskPair, 8> LiveUses;
+    SmallVector<VRegMaskOrUnit, 8> LiveUses;
     BotRPTracker.recede(&LiveUses);
     updatePressureDiffs(LiveUses);
   }
@@ -1352,9 +1352,8 @@ updateScheduledPressure(const SUnit *SU,
 
 /// Update the PressureDiff array for liveness after scheduling this
 /// instruction.
-void ScheduleDAGMILive::updatePressureDiffs(
-    ArrayRef<RegisterMaskPair> LiveUses) {
-  for (const RegisterMaskPair &P : LiveUses) {
+void ScheduleDAGMILive::updatePressureDiffs(ArrayRef<VRegMaskOrUnit> LiveUses) {
+  for (const VRegMaskOrUnit &P : LiveUses) {
     Register Reg = P.RegUnit;
     /// FIXME: Currently assuming single-use physregs.
     if (!Reg.isVirtual())
@@ -1579,7 +1578,7 @@ unsigned ScheduleDAGMILive::computeCyclicCriticalPath() {
 
   unsigned MaxCyclicLatency = 0;
   // Visit each live out vreg def to find def/use pairs that cross iterations.
-  for (const RegisterMaskPair &P : RPTracker.getPressure().LiveOutRegs) {
+  for (const VRegMaskOrUnit &P : RPTracker.getPressure().LiveOutRegs) {
     Register Reg = P.RegUnit;
     if (!Reg.isVirtual())
       continue;
@@ -1707,7 +1706,7 @@ void ScheduleDAGMILive::scheduleMI(SUnit *SU, bool IsTopNode) {
 
       if (BotRPTracker.getPos() != CurrentBottom)
         BotRPTracker.recedeSkipDebugValues();
-      SmallVector<RegisterMaskPair, 8> LiveUses;
+      SmallVector<VRegMaskOrUnit, 8> LiveUses;
       BotRPTracker.recede(RegOpers, &LiveUses);
       assert(BotRPTracker.getPos() == CurrentBottom && "out of sync");
       LLVM_DEBUG(dbgs() << "Bottom Pressure:\n"; dumpRegSetPressure(
diff --git a/llvm/lib/CodeGen/RegisterPressure.cpp b/llvm/lib/CodeGen/RegisterPressure.cpp
index 037986ec48af..e8e6db1e3b3b 100644
--- a/llvm/lib/CodeGen/RegisterPressure.cpp
+++ b/llvm/lib/CodeGen/RegisterPressure.cpp
@@ -95,7 +95,7 @@ void RegisterPressure::dump(const TargetRegisterInfo *TRI) const {
   dbgs() << "Max Pressure: ";
   dumpRegSetPressure(MaxSetPressure, TRI);
   dbgs() << "Live In: ";
-  for (const RegisterMaskPair &P : LiveInRegs) {
+  for (const VRegMaskOrUnit &P : LiveInRegs) {
     dbgs() << printVRegOrUnit(P.RegUnit, TRI);
     if (!P.LaneMask.all())
       dbgs() << ':' << PrintLaneMask(P.LaneMask);
@@ -103,7 +103,7 @@ void RegisterPressure::dump(const TargetRegisterInfo *TRI) const {
   }
   dbgs() << '\n';
   dbgs() << "Live Out: ";
-  for (const RegisterMaskPair &P : LiveOutRegs) {
+  for (const VRegMaskOrUnit &P : LiveOutRegs) {
     dbgs() << printVRegOrUnit(P.RegUnit, TRI);
     if (!P.LaneMask.all())
       dbgs() << ':' << PrintLaneMask(P.LaneMask);
@@ -358,7 +358,7 @@ void RegPressureTracker::closeRegion() {
 void RegPressureTracker::initLiveThru(const RegPressureTracker &RPTracker) {
   LiveThruPressure.assign(TRI->getNumRegPressureSets(), 0);
   assert(isBottomClosed() && "need bottom-up tracking to intialize.");
-  for (const RegisterMaskPair &Pair : P.LiveOutRegs) {
+  for (const VRegMaskOrUnit &Pair : P.LiveOutRegs) {
     Register RegUnit = Pair.RegUnit;
     if (RegUnit.isVirtual() && !RPTracker.hasUntiedDef(RegUnit))
       increaseSetPressure(LiveThruPressure, *MRI, RegUnit,
@@ -366,9 +366,9 @@ void RegPressureTracker::initLiveThru(const RegPressureTracker &RPTracker) {
   }
 }
 
-static LaneBitmask getRegLanes(ArrayRef<RegisterMaskPair> RegUnits,
+static LaneBitmask getRegLanes(ArrayRef<VRegMaskOrUnit> RegUnits,
                                Register RegUnit) {
-  auto I = llvm::find_if(RegUnits, [RegUnit](const RegisterMaskPair Other) {
+  auto I = llvm::find_if(RegUnits, [RegUnit](const VRegMaskOrUnit Other) {
     return Other.RegUnit == RegUnit;
   });
   if (I == RegUnits.end())
@@ -376,11 +376,11 @@ static LaneBitmask getRegLanes(ArrayRef<RegisterMaskPair> RegUnits,
   return I->LaneMask;
 }
 
-static void addRegLanes(SmallVectorImpl<RegisterMaskPair> &RegUnits,
-                        RegisterMaskPair Pair) {
+static void addRegLanes(SmallVectorImpl<VRegMaskOrUnit> &RegUnits,
+                        VRegMaskOrUnit Pair) {
   Register RegUnit = Pair.RegUnit;
   assert(Pair.LaneMask.any());
-  auto I = llvm::find_if(RegUnits, [RegUnit](const RegisterMaskPair Other) {
+  auto I = llvm::find_if(RegUnits, [RegUnit](const VRegMaskOrUnit Other) {
     return Other.RegUnit == RegUnit;
   });
   if (I == RegUnits.end()) {
@@ -390,23 +390,23 @@ static void addRegLanes(SmallVectorImpl<RegisterMaskPair> &RegUnits,
   }
 }
 
-static void setRegZero(SmallVectorImpl<RegisterMaskPair> &RegUnits,
+static void setRegZero(SmallVectorImpl<VRegMaskOrUnit> &RegUnits,
                        Register RegUnit) {
-  auto I = llvm::find_if(RegUnits, [RegUnit](const RegisterMaskPair Other) {
+  auto I = llvm::find_if(RegUnits, [RegUnit](const VRegMaskOrUnit Other) {
     return Other.RegUnit == RegUnit;
   });
   if (I == RegUnits.end()) {
-    RegUnits.push_back(RegisterMaskPair(RegUnit, LaneBitmask::getNone()));
+    RegUnits.emplace_back(RegUnit, LaneBitmask::getNone());
   } else {
     I->LaneMask = LaneBitmask::getNone();
   }
 }
 
-static void removeRegLanes(SmallVectorImpl<RegisterMaskPair> &RegUnits,
-                           RegisterMaskPair Pair) {
+static void removeRegLanes(SmallVectorImpl<VRegMaskOrUnit> &RegUnits,
+                           VRegMaskOrUnit Pair) {
   Register RegUnit = Pair.RegUnit;
   assert(Pair.LaneMask.any());
-  auto I = llvm::find_if(RegUnits, [RegUnit](const RegisterMaskPair Other) {
+  auto I = llvm::find_if(RegUnits, [RegUnit](const VRegMaskOrUnit Other) {
     return Other.RegUnit == RegUnit;
   });
   if (I != RegUnits.end()) {
@@ -480,7 +480,7 @@ class RegisterOperandsCollector {
       collectOperand(*OperI);
 
     // Remove redundant physreg dead defs.
-    for (const RegisterMaskPair &P : RegOpers.Defs)
+    for (const VRegMaskOrUnit &P : RegOpers.Defs)
       removeRegLanes(RegOpers.DeadDefs, P);
   }
 
@@ -489,7 +489,7 @@ class RegisterOperandsCollector {
       collectOperandLanes(*OperI);
 
     // Remove redundant physreg dead defs.
-    for (const RegisterMaskPair &P : RegOpers.Defs)
+    for (const VRegMaskOrUnit &P : RegOpers.Defs)
       removeRegLanes(RegOpers.DeadDefs, P);
   }
 
@@ -515,13 +515,12 @@ class RegisterOperandsCollector {
     }
   }
 
-  void pushReg(Register Reg,
-               SmallVectorImpl<RegisterMaskPair> &RegUnits) const {
+  void pushReg(Register Reg, SmallVectorImpl<VRegMaskOrUnit> &RegUnits) const {
     if (Reg.isVirtual()) {
-      addRegLanes(RegUnits, RegisterMaskPair(Reg, LaneBitmask::getAll()));
+      addRegLanes(RegUnits, VRegMaskOrUnit(Reg, LaneBitmask::getAll()));
     } else if (MRI.isAllocatable(Reg)) {
       for (MCRegUnit Unit : TRI.regunits(Reg.asMCReg()))
-        addRegLanes(RegUnits, RegisterMaskPair(Unit, LaneBitmask::getAll()));
+        addRegLanes(RegUnits, VRegMaskOrUnit(Unit, LaneBitmask::getAll()));
     }
   }
 
@@ -548,15 +547,15 @@ class RegisterOperandsCollector {
   }
 
   void pushRegLanes(Register Reg, unsigned SubRegIdx,
-                    SmallVectorImpl<RegisterMaskPair> &RegUnits) const {
+                    SmallVectorImpl<VRegMaskOrUnit> &RegUnits) const {
     if (Reg.isVirtual()) {
       LaneBitmask LaneMask = SubRegIdx != 0
                              ? TRI.getSubRegIndexLaneMask(SubRegIdx)
                              : MRI.getMaxLaneMaskForVReg(Reg);
-      addRegLanes(RegUnits, RegisterMaskPair(Reg, LaneMask));
+      addRegLanes(RegUnits, VRegMaskOrUnit(Reg, LaneMask));
     } else if (MRI.isAllocatable(Reg)) {
       for (MCRegUnit Unit : TRI.regunits(Reg.asMCReg()))
-        addRegLanes(RegUnits, RegisterMaskPair(Unit, LaneBitmask::getAll()));
+        addRegLanes(RegUnits, VRegMaskOrUnit(Unit, LaneBitmask::getAll()));
     }
   }
 };
@@ -622,7 +621,7 @@ void RegisterOperands::adjustLaneLiveness(const LiveIntervals &LIS,
     LaneMask = getLiveLanesAt(LIS, MRI, true, RegUnit, Pos.getBaseIndex());
 
   if (AddFlagsMI != nullptr) {
-    for (const RegisterMaskPair &P : DeadDefs) {
+    for (const VRegMaskOrUnit &P : DeadDefs) {
       Register RegUnit = P.RegUnit;
       if (!RegUnit.isVirtual())
         continue;
@@ -651,10 +650,10 @@ void PressureDiffs::addInstruction(unsigned Idx,
                                    const MachineRegisterInfo &MRI) {
   PressureDiff &PDiff = (*this)[Idx];
   assert(!PDiff.begin()->isValid() && "stale PDiff");
-  for (const RegisterMaskPair &P : RegOpers.Defs)
+  for (const VRegMaskOrUnit &P : RegOpers.Defs)
     PDiff.addPressureChange(P.RegUnit, true, &MRI);
 
-  for (const RegisterMaskPair &P : RegOpers.Uses)
+  for (const VRegMaskOrUnit &P : RegOpers.Uses)
     PDiff.addPressureChange(P.RegUnit, false, &MRI);
 }
 
@@ -694,20 +693,20 @@ void PressureDiff::addPressureChange(Register RegUnit, bool IsDec,
 }
 
 /// Force liveness of registers.
-void RegPressureTracker::addLiveRegs(ArrayRef<RegisterMaskPair> Regs) {
-  for (const RegisterMaskPair &P : Regs) {
+void RegPressureTracker::addLiveRegs(ArrayRef<VRegMaskOrUnit> Regs) {
+  for (const VRegMaskOrUnit &P : Regs) {
     LaneBitmask PrevMask = LiveRegs.insert(P);
     LaneBitmask NewMask = PrevMask | P.LaneMask;
     increaseRegPressure(P.RegUnit, PrevMask, NewMask);
   }
 }
 
-void RegPressureTracker::discoverLiveInOrOut(RegisterMaskPair Pair,
-    SmallVectorImpl<RegisterMaskPair> &LiveInOrOut) {
+void RegPressureTracker::discoverLiveInOrOut(
+    VRegMaskOrUnit Pair, SmallVectorImpl<VRegMaskOrUnit> &LiveInOrOut) {
   assert(Pair.LaneMask.any());
 
   Register RegUnit = Pair.RegUnit;
-  auto I = llvm::find_if(LiveInOrOut, [RegUnit](const RegisterMaskPair &Other) {
+  auto I = llvm::find_if(LiveInOrOut, [RegUnit](const VRegMaskOrUnit &Other) {
     return Other.RegUnit == RegUnit;
   });
   LaneBitmask PrevMask;
@@ -724,22 +723,22 @@ void RegPressureTracker::discoverLiveInOrOut(RegisterMaskPair Pair,
   increaseSetPressure(P.MaxSetPressure, *MRI, RegUnit, PrevMask, NewMask);
 }
 
-void RegPressureTracker::discoverLiveIn(RegisterMaskPair Pair) {
+void RegPressureTracker::discoverLiveIn(VRegMaskOrUnit Pair) {
   discoverLiveInOrOut(Pair, P.LiveInRegs);
 }
 
-void RegPressureTracker::discoverLiveOut(RegisterMaskPair Pair) {
+void RegPressureTracker::discoverLiveOut(VRegMaskOrUnit Pair) {
   discoverLiveInOrOut(Pair, P.LiveOutRegs);
 }
 
-void RegPressureTracker::bumpDeadDefs(ArrayRef<RegisterMaskPair> DeadDefs) {
-  for (const RegisterMaskPair &P : DeadDefs) {
+void RegPressureTracker::bumpDeadDefs(ArrayRef<VRegMaskOrUnit> DeadDefs) {
+  for (const VRegMaskOrUnit &P : DeadDefs) {
     Register Reg = P.RegUnit;
     LaneBitmask LiveMask = LiveRegs.contains(Reg);
     LaneBitmask BumpedMask = LiveMask | P.LaneMask;
     increaseRegPressure(Reg, LiveMask, BumpedMask);
   }
-  for (const RegisterMaskPair &P : DeadDefs) {
+  for (const VRegMaskOrUnit &P : DeadDefs) {
     Register Reg = P.RegUnit;
     LaneBitmask LiveMask = LiveRegs.contains(Reg);
     LaneBitmask BumpedMask = LiveMask | P.LaneMask;
@@ -753,7 +752,7 @@ void RegPressureTracker::bumpDeadDefs(ArrayRef<RegisterMaskPair> DeadDefs) {
 /// difference pointer is provided record the changes is pressure caused by this
 /// instruction independent of liveness.
 void RegPressureTracker::recede(const RegisterOperands &RegOpers,
-                                SmallVectorImpl<RegisterMaskPair> *LiveUses) {
+                                SmallVectorImpl<VRegMaskOrUnit> *LiveUses) {
   assert(!CurrPos->isDebugOrPseudoInstr());
 
   // Boost pressure for all dead defs together.
@@ -761,7 +760,7 @@ void RegPressureTracker::recede(const RegisterOperands &RegOpers,
 
   // Kill liveness at live defs.
   // TODO: consider earlyclobbers?
-  for (const RegisterMaskPair &Def : RegOpers.Defs) {
+  for (const VRegMaskOrUnit &Def : RegOpers.Defs) {
     Register Reg = Def.RegUnit;
 
     LaneBitmask PreviousMask = LiveRegs.erase(Def);
@@ -769,7 +768,7 @@ void RegPressureTracker::recede(const RegisterOperands &RegOpers,
 
     LaneBitmask LiveOut = Def.LaneMask & ~PreviousMask;
     if (LiveOut.any()) {
-      discoverLiveOut(RegisterMaskPair(Reg, LiveOut));
+      discoverLiveOut(VRegMaskOrUnit(Reg, LiveOut));
       // Retroactively model effects on pressure of the live out lanes.
       increaseSetPressure(CurrSetPressure, *MRI, Reg, LaneBitmask::getNone(),
                           LiveOut);
@@ -791,7 +790,7 @@ void RegPressureTracker::recede(const RegisterOperands &RegOpers,
     SlotIdx = LIS->getInstructionIndex(*CurrPos).getRegSlot();
 
   // Generate liveness for uses.
-  for (const RegisterMaskPair &Use : RegOpers.Uses) {
+  for (const VRegMaskOrUnit &Use : RegOpers.Uses) {
     Register Reg = Use.RegUnit;
     assert(Use.LaneMask.any());
     LaneBitmask PreviousMask = LiveRegs.insert(Use);
@@ -803,19 +802,18 @@ void RegPressureTracker::recede(const RegisterOperands &RegOpers,
     if (PreviousMask.none()) {
       if (LiveUses != nullptr) {
         if (!TrackLaneMasks) {
-          addRegLanes(*LiveUses, RegisterMaskPair(Reg, NewMask));
+          addRegLanes(*LiveUses, VRegMaskOrUnit(Reg, NewMask));
         } else {
-          auto I =
-              llvm::find_if(*LiveUses, [Reg](const RegisterMaskPair Other) {
-                return Other.RegUnit == Reg;
-              });
+          auto I = llvm::find_if(*LiveUses, [Reg](const VRegMaskOrUnit Other) {
+            return Other.RegUnit == Reg;
+          });
           bool IsRedef = I != LiveUses->end();
           if (IsRedef) {
             // ignore re-defs here...
             assert(I->LaneMask.none());
-            removeRegLanes(*LiveUses, RegisterMaskPair(Reg, NewMask));
+            removeRegLanes(*LiveUses, VRegMaskOrUnit(Reg, NewMask));
           } else {
-            addRegLanes(*LiveUses, RegisterMaskPair(Reg, NewMask));
+            addRegLanes(*LiveUses, VRegMaskOrUnit(Reg, NewMask));
           }
         }
       }
@@ -824,14 +822,14 @@ void RegPressureTracker::recede(const RegisterOperands &RegOpers,
       if (RequireIntervals) {
         LaneBitmask LiveOut = getLiveThroughAt(Reg, SlotIdx);
         if (LiveOut.any())
-          discoverLiveOut(RegisterMaskPair(Reg, LiveOut));
+          discoverLiveOut(VRegMaskOrUnit(Reg, LiveOut));
       }
     }
 
     increaseRegPressure(Reg, PreviousMask, NewMask);
   }
   if (TrackUntiedDefs) {
-    for (const RegisterMaskPair &Def : RegOpers.Defs) {
+    for (const VRegMaskOrUnit &Def : RegOpers.Defs) {
       Register RegUnit = Def.RegUnit;
       if (RegUnit.isVirtual() &&
           (LiveRegs.contains(RegUnit) & Def.LaneMask).none())
@@ -861,7 +859,7 @@ void RegPressureTracker::recedeSkipDebugValues() {
     static_cast<IntervalPressure&>(P).openTop(SlotIdx);
 }
 
-void RegPressureTracker::recede(SmallVectorImpl<RegisterMaskPair> *LiveUses) {
+void RegPressureTracker::recede(SmallVectorImpl<VRegMaskOrUnit> *LiveUses) {
   recedeSkipDebugValues();
   if (CurrPos->isDebugInstr() || CurrPos->isPseudoProbe()) {
     // It's possible to only have debug_value and pseudo probe instructions and
@@ -902,27 +900,27 @@ void RegPressureTracker::advance(const RegisterOperands &RegOpers) {
       static_cast<RegionPressure&>(P).openBottom(CurrPos);
   }
 
-  for (const RegisterMaskPair &Use : RegOpers.Uses) {
+  for (const VRegMaskOrUnit &Use : RegOpers.Uses) {
     Register Reg = Use.RegUnit;
     LaneBitmask LiveMask = LiveRegs.contains(Reg);
     LaneBitmask LiveIn = Use.LaneMask & ~LiveMask;
     if (LiveIn.any()) {
-      discoverLiveIn(RegisterMaskPair(Reg, LiveIn));
+      discoverLiveIn(VRegMaskOrUnit(Reg, LiveIn));
       increaseRegPressure(Reg, LiveMask, LiveMask | LiveIn);
-      LiveRegs.insert(RegisterMaskPair(Reg, LiveIn));
+      LiveRegs.insert(VRegMaskOrUnit(Reg, LiveIn));
     }
     // Kill liveness at last uses.
     if (RequireIntervals) {
       LaneBitmask LastUseMask = getLastUsedLanes(Reg, SlotIdx);
       if (LastUseMask.any()) {
-        LiveRegs.erase(RegisterMaskPair(Reg, LastUseMask));
+        LiveRegs.erase(VRegMaskOrUnit(Reg, LastUseMask));
         decreaseRegPressure(Reg, LiveMask, LiveMask & ~LastUseMask);
       }
     }
   }
 
   // Generate liveness for defs.
-  for (const RegisterMaskPair &Def : RegOpers.Defs) {
+  for (const VRegMaskOrUnit &Def : RegOpers.Defs) {
     LaneBitmask PreviousMask = LiveRegs.insert(Def);
     LaneBitmask NewMask = PreviousMask | Def.LaneMask;
     increaseRegPressure(Def.RegUnit, PreviousMask, NewMask);
@@ -1051,7 +1049,7 @@ void RegPressureTracker::bumpUpwardPressure(const MachineInstr *MI) {
   bumpDeadDefs(RegOpers.DeadDefs);
 
   // Kill liveness at live defs.
-  for (const RegisterMaskPair &P : RegOpers.Defs) {
+  for (const VRegMaskOrUnit &P : RegOpers.Defs) {
     Register Reg = P.RegUnit;
     LaneBitmask LiveAfter = LiveRegs.contains(Reg);
     LaneBitmask UseLanes = getRegLanes(RegOpers.Uses, Reg);
@@ -1063,7 +1061,7 @@ void RegPressureTracker::bumpUpwardPressure(const MachineInstr *MI) {
     decreaseRegPressure(Reg, LiveAfter, LiveAfter & LiveBefore);
   }
   // Generate liveness for uses. Also handle any uses which overlap with defs.
-  for (const RegisterMaskPair &P : RegOpers.Uses) {
+  for (const VRegMaskOrUnit &P : RegOpers.Uses) {
     Register Reg = P.RegUnit;
     LaneBitmask LiveAfter = LiveRegs.contains(Reg);
     LaneBitmask LiveBefore = LiveAfter | P.LaneMask;
@@ -1288,7 +1286,7 @@ void RegPressureTracker::bumpDownwardPressure(const MachineInstr *MI) {
     RegOpers.adjustLaneLiveness(*LIS, *MRI, SlotIdx);
 
   if (RequireIntervals) {
-    for (const RegisterMaskPair &Use : RegOpers.Uses) {
+    for (const VRegMaskOrUnit &Use : RegOpers.Uses) {
       Register Reg = Use.RegUnit;
       LaneBitmask LastUseMask = getLastUsedLanes(Reg, SlotIdx);
       if (LastUseMask.none())
@@ -1311,7 +1309,7 @@ void RegPressureTracker::bumpDownwardPressure(const MachineInstr *MI) {
   }
 
   // Generate liveness for defs.
-  for (const RegisterMaskPair &Def : RegOpers.Defs) {
+  for (const VRegMaskOrUnit &Def : RegOpers.Defs) {
     Register Reg = Def.RegUnit;
     LaneBitmask LiveMask = LiveRegs.contains(Reg);
     LaneBitmask NewMask = LiveMask | Def.LaneMask;
diff --git a/llvm/lib/Target/AMDGPU/GCNRegPressure.cpp b/llvm/lib/Target/AMDGPU/GCNRegPressure.cpp
index d46c4cf23a22..a438ad00bc41 100644
--- a/llvm/lib/Target/AMDGPU/GCNRegPressure.cpp
+++ b/llvm/lib/Target/AMDGPU/GCNRegPressure.cpp
@@ -256,7 +256,7 @@ static LaneBitmask getDefRegMask(const MachineOperand &MO,
 }
 
 static void
-collectVirtualRegUses(SmallVectorImpl<RegisterMaskPair> &RegMaskPairs,
+collectVirtualRegUses(SmallVectorImpl<VRegMaskOrUnit> &VRegMaskOrUnits,
                       const MachineInstr &MI, const LiveIntervals &LIS,
                       const MachineRegisterInfo &MRI) {
 
@@ -268,12 +268,12 @@ collectVirtualRegUses(SmallVectorImpl<RegisterMaskPair> &RegMaskPairs,
       continue;
 
     Register Reg = MO.getReg();
-    auto I = llvm::find_if(RegMaskPairs, [Reg](const RegisterMaskPair &RM) {
+    auto I = llvm::find_if(VRegMaskOrUnits, [Reg](const VRegMaskOrUnit &RM) {
       return RM.RegUnit == Reg;
     });
 
-    auto &P = I == RegMaskPairs.end()
-                  ? RegMaskPairs.emplace_back(Reg, LaneBitmask::getNone())
+    auto &P = I == VRegMaskOrUnits.end()
+                  ? VRegMaskOrUnits.emplace_back(Reg, LaneBitmask::getNone())
                   : *I;
 
     P.LaneMask |= MO.getSubReg() ? TRI.getSubRegIndexLaneMask(MO.getSubReg())
@@ -281,7 +281,7 @@ collectVirtualRegUses(SmallVectorImpl<RegisterMaskPair> &RegMaskPairs,
   }
 
   SlotIndex InstrSI;
-  for (auto &P : RegMaskPairs) {
+  for (auto &P : VRegMaskOrUnits) {
     auto &LI = LIS.getInterval(P.RegUnit);
     if (!LI.hasSubRanges())
       continue;
@@ -477,9 +477,9 @@ void GCNUpwardRPTracker::recede(const MachineInstr &MI) {
   MaxPressure = max(DefPressure, MaxPressure);
 
   // Make uses alive.
-  SmallVector<RegisterMaskPair, 8> RegUses;
+  SmallVector<VRegMaskOrUnit, 8> RegUses;
   collectVirtualRegUses(RegUses, MI, LIS, *MRI);
-  for (const RegisterMaskPair &U : RegUses) {
+  for (const VRegMaskOrUnit &U : RegUses) {
     LaneBitmask &LiveMask = LiveRegs[U.RegUnit];
     LaneBitmask PrevMask = LiveMask;
     LiveMask |= U.LaneMask;
@@ -665,7 +665,7 @@ GCNDownwardRPTracker::bumpDownwardPressure(const MachineInstr *MI,
   RegOpers.adjustLaneLiveness(LIS, *MRI, SlotIdx);
   GCNRegPressure TempPressure = CurPressure;
 
-  for (const RegisterMaskPair &Use : RegOpers.Uses) {
+  for (const VRegMaskOrUnit &Use : RegOpers.Uses) {
     Register Reg = Use.RegUnit;
     if (!Reg.isVirtual())
       continue;
@@ -699,7 +699,7 @@ GCNDownwardRPTracker::bumpDownwardPressure(const MachineInstr *MI,
   }
 
   // Generate liveness for defs.
-  for (const RegisterMaskPair &Def : RegOpers.Defs) {
+  for (const VRegMaskOrUnit &Def : RegOpers.Defs) {
     Register Reg = Def.RegUnit;
     if (!Reg.isVirtual())
       continue;
@@ -908,4 +908,4 @@ bool GCNRegPressurePrinter::runOnMachineFunction(MachineFunction &MF) {
   return false;
 
 #undef PFX
-}
\ No newline at end of file
+}
diff --git a/llvm/lib/Target/AMDGPU/GCNRegPressure.h b/llvm/lib/Target/AMDGPU/GCNRegPressure.h
index 06c3d9027db1..7554b9f578fc 100644
--- a/llvm/lib/Target/AMDGPU/GCNRegPressure.h
+++ b/llvm/lib/Target/AMDGPU/GCNRegPressure.h
@@ -170,7 +170,7 @@ protected:
              bool After);
 
   /// Mostly copy/paste from CodeGen/RegisterPressure.cpp
-  void bumpDeadDefs(ArrayRef<RegisterMaskPair> DeadDefs);
+  void bumpDeadDefs(ArrayRef<VRegMaskOrUnit> DeadDefs);
 
   LaneBitmask getLastUsedLanes(Register RegUnit, SlotIndex Pos) const;