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path: root/llvm/test/CodeGen/X86/bitreverse.ll
AgeCommit message (Expand)Author
2024-10-24[X86] ReplaceNodeResults - adjust assert to allow XOP or GFNI subtargets to s...Simon Pilgrim
2024-07-18[X86] getGFNICtrlMask - create a vXi8 mask instead of a bitcasted vXi64 mask.Simon Pilgrim
2024-04-15Support for i8/i16 for bitreverse using GFNI. (#88625)shamithoke
2024-04-10Perform bitreverse using AVX512 GFNI for i32 and i64. (#81764)shamithoke
2024-01-24[X86] X86FixupVectorConstants - shrink vector load to movsd/movsd/movd/movq '...Simon Pilgrim
2024-01-23[MC][X86] Merge lane/element broadcast comment printers. (#79020)Simon Pilgrim
2023-10-09Revert "[CodeGen] Really renumber slot indexes before register allocation (#6...Jay Foad
2023-10-09[CodeGen] Really renumber slot indexes before register allocation (#67038)Jay Foad
2023-09-19[CodeGen] Renumber slot indexes before register allocation (#66334)Jay Foad
2023-06-13[X86] X86FixupVectorConstantsPass - attempt to replace full width fp vector c...Simon Pilgrim
2023-06-06Revert rG98061013e01207444cfd3980 - [X86] X86FixupVectorConstantsPass - attem...Simon Pilgrim
2023-05-29[X86] X86FixupVectorConstantsPass - attempt to replace full width fp vector c...Simon Pilgrim
2022-09-30X86: Stop assigning register costs for longer encodings.Matthias Braun
2022-09-13[X86] Add GFNI test coverage for bitreverse codegenSimon Pilgrim
2022-07-28[DAG] Enable ISD::SRL SimplifyMultipleUseDemandedBits handling inside Simplif...Simon Pilgrim
2022-07-19[x86] use zero-extending load of a byte outside of loops too (2nd try)Sanjay Patel
2022-07-19Revert "[x86] use zero-extending load of a byte outside of loops too"Sanjay Patel
2022-07-19[x86] use zero-extending load of a byte outside of loops tooSanjay Patel
2022-06-02[ValueTypes] Define MVTs for v128i2/v64i4 as well as i2 and i4.Hendrik Greving
2022-06-01Revert "[ValueTypes] Define MVTs for v128i2/v64i4 as well as i2 and i4."Hendrik Greving
2022-06-01[ValueTypes] Define MVTs for v128i2/v64i4 as well as i2 and i4.Hendrik Greving
2021-11-29[TwoAddressInstructionPass] Create register mapping for registers with multip...Guozhi Wei
2021-10-21[LegalizeVectorOps][X86] Don't defer BITREVERSE expansion to LegalizeDAG.Craig Topper
2021-10-11[TwoAddressInstructionPass] Improve the SrcRegMap and DstRegMap computationGuozhi Wei
2021-09-14RegAllocGreedy: Account for reserved registers in num regs heuristicMatt Arsenault
2021-08-26[SelectionDAG] Optimize bitreverse expansion to minimize the number of mask c...Craig Topper
2021-08-24[X86] Freeze vXi8 shl(x,1) -> add(x,x) vector fold (PR50468)Simon Pilgrim
2021-06-11[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were alr...Roman Lebedev
2021-03-28[X86][update_llc_test_checks] Use a less greedy regular expression for replac...Craig Topper
2020-11-15[X86] Fix crash with i64 bitreverse on 32-bit targets with XOP.Craig Topper
2020-02-14[X86][SSE] lowerShuffleAsBitRotate - lower to vXi8 shuffles to ROTL on pre-SS...Simon Pilgrim
2020-02-12Revert "[X86][SSE] lowerShuffleAsBitRotate - lower to vXi8 shuffles to ROTL o...Amy Huang
2020-02-11[X86][SSE] lowerShuffleAsBitRotate - lower to vXi8 shuffles to ROTL on pre-SS...Simon Pilgrim
2019-08-07Recommit r367901 "[X86] Enable -x86-experimental-vector-widening-legalization...Craig Topper
2019-08-06Revert "[X86] Enable -x86-experimental-vector-widening-legalization by default."Mitch Phillips
2019-08-05[X86] Enable -x86-experimental-vector-widening-legalization by default.Craig Topper
2019-05-25[X86FixupLEAs] Turn optIncDec into a generic two address LEA optimizer. Suppo...Craig Topper
2019-05-24[SelectionDAG] computeKnownBits - support constant pool values from targetSimon Pilgrim
2019-03-05[X86] Enable 8-bit OR with disjoint bits to convert to LEACraig Topper
2019-01-22[X86][SSE] Canonicalize OR(AND(X,C),AND(Y,~C)) -> OR(AND(X,C),ANDNP(C,Y))Simon Pilgrim
2018-10-13[LegalizeTypes] Prevent an assertion from PromoteIntRes_BSWAP and PromoteIntR...Craig Topper
2018-09-19[X86] Handle COPYs of physregs better (regalloc hints)Simon Pilgrim
2018-01-31Followup on Proposal to move MIR physical register namespace to '$' sigil.Puyan Lotfi
2017-12-07[CodeGen] Use MachineOperand::print in the MIRPrinter for MO_Register.Francis Visoiu Mistrih
2017-12-04[CodeGen] Unify MBB reference format in both MIR and debug outputFrancis Visoiu Mistrih
2017-11-28[CodeGen] Print register names in lowercase in both MIR and debug outputFrancis Visoiu Mistrih
2017-09-18[X86FixupBWInsts] More precise register liveness if no <imp-use> on MOVs.Nikolai Bozhenov
2017-03-14[X86] Add extra BITREVERSE testsSimon Pilgrim
2016-07-22[SelectionDAG] Optimization of BITREVERSE legalization for power-of-2 integer...Simon Pilgrim
2016-07-09VirtRegMap: Replace some identity copies with KILL instructions.Matthias Braun
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