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AgeCommit message (Expand)Author
2025-11-14[Sparc] Optimize compare instruction (#167140)Koakuma
2025-11-06[SPARC] Mark branches as being expensive in early Niagara CPUs (#166489)Koakuma
2025-10-08[SPARC] Weaken emitted barriers for atomic ops (#154950)Koakuma
2025-10-03[SPARC] Prevent meta instructions from being inserted into delay slots (#161111)Koakuma
2025-09-26[clang][SPARC] Pass 16-aligned structs with the correct alignment in CC (#155...Koakuma
2025-08-18[SPARC] Change `half` to use soft promotion rather than `PromoteFloat` (#152...Trevor Gross
2025-08-12[SPARC] Use FMA instructions when we have UA2007 (#148434)Koakuma
2025-08-12[SPARC] Add a test for `half` support (NFC) (#152723)Trevor Gross
2025-08-12[Test] Add and update tests for `lrint`/`llrint` (NFC) (#152662)Trevor Gross
2025-07-22[Sparc] Remove bogus stack adjustment for LD/GD TLS (#149890)Jessica Clarke
2025-07-22[NFC][Sparc] Pre-commit a test showing inefficient and broken LD/GD TLSJessica Clarke
2025-07-15RuntimeLibcalls: Add some tests for OpenBSD stack protectors (#147888)Matt Arsenault
2025-07-14SPARC: Add gnu run line to sincos test (#147714)Matt Arsenault
2025-07-09SPARC: Add sincos intrinsic test (#147464)Matt Arsenault
2025-06-23CodeGen: Emit error if getRegisterByName fails (#145194)Matt Arsenault
2025-06-20[SPARC][IAS] Properly set implied feature sets for ISA levels/extensions (#14...Koakuma
2025-05-23[SPARC] Use op-then-halve instructions when we have VIS3Koakuma
2025-05-06 [SPARC] Use op-then-neg instructions when we have VIS3 (#138603)Koakuma
2025-05-05Sparc: Improve SETHI and R_SPARC_DISP32 testsFangrui Song
2025-04-29[CGP] Despeculate ctlz/cttz with "illegal" integer types (#137197)Sergei Barannikov
2025-04-26[SPARC] Promote i32 CTTZ when we have VIS3Koakuma
2025-04-22Reapply "[SPARC] Use umulxhi to do extending 64x64->128 multiply when we have...Koakuma
2025-04-17[SPARC] Use native bitcast instructions when we have VIS3Koakuma
2025-04-17[SPARC] Use lzcnt to implement CTLZ when we have VIS3Koakuma
2025-04-16Revert "[SPARC] Use umulxhi to do extending 64x64->128 multiply when we have ...Koakuma
2025-04-16[SPARC] Use umulxhi to do extending 64x64->128 multiply when we have VIS3Koakuma
2025-04-16[SPARC] Use addxccc to do multiword addition when we have VIS3Koakuma
2025-04-16[SPARC] Use fzero/fzeros to materialize FP zeros when we have VISKoakuma
2025-04-14[RegAlloc] Sort CopyHint by IsCSR (#131046)Michael Maitland
2025-02-19[CodeGen] Use __extendhfsf2 and __truncsfhf2 by default (#126880)Nikita Popov
2025-02-05PeepholeOpt: Fix looking for def of current copy to coalesce (#125533)Matt Arsenault
2025-01-23[TargetLowering] Improve one signature of forceExpandWideMUL. (#123991)Craig Topper
2025-01-18[LegalizeIntegerTypes] Use forceExpandWideMUL in ExpandIntRes_XMULO. (#123432)Craig Topper
2024-12-15[Sparc,test] Change llc -march= to -mtriple=Fangrui Song
2024-11-03[SPARC] Allow overaligned `alloca`s (#107223)Koakuma
2024-10-19[llvm] Ensure that soft float targets don't emit `fma()` libcalls. (#106615)Alex Rønne Petersen
2024-10-18[llvm] Consistently respect `naked` fn attribute in `TargetFrameLowering::has...Alex Rønne Petersen
2024-10-02DAG: Preserve disjoint flag when emitting final instructions (#110795)Matt Arsenault
2024-09-30[SPARC] Align i128 to 16 bytes in SPARC datalayouts (#106951)Koakuma
2024-09-24[ISelDAG] Salvage debug info at isel by referring to frame indices. (#109126)Bevin Hansson
2024-08-20[SPARC] Remove assertions in printOperand for inline asm operands (#104692)Koakuma
2024-08-19[Sparc] Add errata workaround pass for GR712RC and UT700 (#103843)Daniel Cederman
2024-07-28[Sparc] Remove custom lowering for ADD[CE] / SUB[CE] (#100861)Sergei Barannikov
2024-07-28[Sparc] Remove custom lowering for SMULO / UMULO (#100858)Sergei Barannikov
2024-06-19[NFC][SPARC] Fix typos and style mismatchesKoakuma
2024-05-13[test] Fix check prefixesFangrui Song
2024-05-03[test] Convert text files from CRLF to LFFangrui Song
2024-04-05[SPARC] Implement L and H inline asm argument modifiers (#87259)Koakuma
2024-02-13[Sparc] limit MaxAtomicSizeInBitsSupported to 32 for 32-bit Sparc. (#81655)James Y Knight
2024-02-11[SPARC] Support reserving arbitrary general purpose registers (#74927)Koakuma
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