| Age | Commit message (Expand) | Author |
|---|
| 2025-11-22 | [RISCV] Support zilsd-4byte-align for i64 load/store in SelectionDAG. (#169182) | Craig Topper |
| 2025-11-23 | Revert "[RegAlloc] Fix the terminal rule check for interfere with DstReg (#16... | Aiden Grossman |
| 2025-11-23 | [RegAlloc] Fix the terminal rule check for interfere with DstReg (#168661) | hstk30-hw |
| 2025-11-22 | [DAGCombiner] Don't optimize insert_vector_elt into shuffle if implicit trunc... | Hongyu Chen |
| 2025-11-21 | [RISCV] Incorporate scalar addends to extend vector multiply accumulate chain... | Ryan Buchner |
| 2025-11-21 | [llvm][RISCV] Implement Zilsd load/store pair optimization (#158640) | Brandon Wu |
| 2025-11-20 | [RISCV] Do not write .s file in a test (#168865) | Mikhail Gudim |
| 2025-11-20 | [RISCV][llvm] Select splat_vector(constant) with PLI (#168204) | Brandon Wu |
| 2025-11-19 | [CFIInserter] Turn a reachable llvm_unreachable into a report_fatal_error. (#... | Craig Topper |
| 2025-11-20 | [RISCV] Only reduce VLs of instructions with demanded VLs (#168693) | Luke Lau |
| 2025-11-19 | [RISCV] Fix CFI Multiple Locations Test (#168772) | Sam Elliott |
| 2025-11-19 | [RISCV][DAGCombiner] Fix potential missed combine in VL->VW extension (#168026) | Kai Lin |
| 2025-11-19 | [AArch64][GlobalISel] Added support for hadd family of intrinsics (#163985) | Joshua Rodriguez |
| 2025-11-19 | [RISCV][test] Add sincos-expansion.ll test case | Alex Bradbury |
| 2025-11-19 | [RISCV][NewPM] Port RISCVCodeGenPrepare to the new pass manager (#168381) | Alex Bradbury |
| 2025-11-18 | [RISCV] Make XFAIL test UNSUPPORTED. (#168525) | Mikhail Gudim |
| 2025-11-18 | [RISCV] Legalize misaligned unmasked vp.load/vp.store to vle8/vse8. (#167745) | Craig Topper |
| 2025-11-18 | [GISel][RISCV] Compute CTPOP of small odd-sized integer correctly (#168559) | Hongyu Chen |
| 2025-11-18 | [DAGCombiner] Fold select into partial.reduce.add operands. (#167857) | Sander de Smalen |
| 2025-11-18 | [RISCV] Add an option to enable CFIInstrInserter. (#164477) | Mikhail Gudim |
| 2025-11-18 | [RISCV] Reduce minimum VL needed for vslidedown.vx in RISCVVLOptimizer (#168392) | Luke Lau |
| 2025-11-17 | [RISCV] Fold Zba-expanded (mul (shr exact X, C1), C2) (#168019) | Piotr Fusik |
| 2025-11-17 | [llvm][RISCV] Support splat and vp_splat for zvfbfa codegen (#167920) | Brandon Wu |
| 2025-11-17 | [VP][RISCV] Enable promotion on fixed-length vp intrinsics with zvfbfmin (#16... | Brandon Wu |
| 2025-11-14 | [llvm][RISCV] Support P extension CodeGen (#167882) | Brandon Wu |
| 2025-11-13 | [RISCV] For (2^N +/- 2^M) muls, prefer ADD to SUB (#166757) | Piotr Fusik |
| 2025-11-14 | [RISCV][llvm] Handle INSERT_VECTOR_ELT, EXTRACT_VECTOR_ELT codegen for zvfbfa... | Brandon Wu |
| 2025-11-13 | [RISCV] Add test for partial reduce with select. NFC | Luke Lau |
| 2025-11-13 | [RISCV] Fix RISCVInsertVSETVLI coalescing clobbering VL def segment (#167712) | Luke Lau |
| 2025-11-12 | [RISCV][GISel] Fallback to SelectionDAG for vleff intrinsics. (#167776) | Craig Topper |
| 2025-11-12 | DAG: Use poison when widening build_vector (#167631) | Matt Arsenault |
| 2025-11-12 | [RISCV] Expand multiplication by `2^N * 3/5/9 + 1` with SHL_ADD (#166933) | Piotr Fusik |
| 2025-11-12 | [RISCV] Add short forward branch support for `lui`, `qc.li`, and `qc.e.li` (#... | quic_hchandel |
| 2025-11-11 | [MachineCopyPropagation] Remove logic to recognise and delete no-op moves pro... | Alex Bradbury |
| 2025-11-11 | [RISCV][llvm] Preliminary P extension codegen support (#162668) | Brandon Wu |
| 2025-11-10 | RISCV: Enable terminal rule (#165961) | Matt Arsenault |
| 2025-11-10 | [DAGCombiner] Add sra-xor-sra pattern fold (#166777) | guan jian |
| 2025-11-11 | MachineCombiner: Partially fix losing subregister indexes (#141661) | Matt Arsenault |
| 2025-11-10 | [CodeGenPrepare] sinkCmpExpression - don't sink larger than legal integer com... | Simon Pilgrim |
| 2025-11-10 | [RISCV][llvm] Support Smpmpmt version 0.6 (#166322) | Brandon Wu |
| 2025-11-10 | [llvm][RISCV] Support Zvfbfa codegen for fneg, fabs and copysign (#166944) | Brandon Wu |
| 2025-11-07 | [RISCV] Support outlining of CFI instructions in the machine outliner (#166149) | Sudharsan Veeravalli |
| 2025-11-06 | [RISCV] Optimize (and (icmp x, 0, neq), (icmp y, 0, neq)) utilizing zicond ex... | Ryan Buchner |
| 2025-11-07 | [RISCV] Use SLLI.UW in double-SHL_ADD multiplications (#166728) | Piotr Fusik |
| 2025-11-07 | [RISCV] Move remat.ll test from riscv32 to riscv64. NFC | Luke Lau |
| 2025-11-06 | [RISCV] More explicitly check that combineOp_VLToVWOp_VL removes the extends ... | Craig Topper |
| 2025-11-06 | [RISCV] Add test cases for widening add/sub with mismatched extends. NFC (#16... | Craig Topper |
| 2025-11-06 | [RISCV] Correct the CFA offsets for stack probing. (#166616) | Craig Topper |
| 2025-11-06 | [RISCV] Shrink deleted dead ADDI's use if coalesced in RISCVInsertVSETVLI (#1... | Luke Lau |
| 2025-11-06 | [DAGCombiner] Bail out if BitWidthDiff > BitWidth when folding cltz(and) - Bi... | Hongyu Chen |
