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path: root/llvm/test/CodeGen/ARM/reg_sequence.ll
AgeCommit message (Expand)Author
2023-06-13[DAGCombine] Make sure combined nodes are added back to the worklist in topol...Amaury Séchet
2023-06-05Revert "[DAGCombine] Make sure combined nodes are added back to the worklist ...JP Lehr
2023-06-05[DAGCombine] Make sure combined nodes are added back to the worklist in topol...Amaury Séchet
2022-12-19[ARM] Convert some tests to opaque pointers (NFC)Nikita Popov
2022-12-05Reapply "[CodeGen] Add new pass for late cleanup of redundant definitions."Jonas Paulsson
2022-12-05Revert "Reapply "[CodeGen] Add new pass for late cleanup of redundant definit...Jonas Paulsson
2022-12-03Reapply "[CodeGen] Add new pass for late cleanup of redundant definitions."Jonas Paulsson
2022-12-01Revert "[CodeGen] Add new pass for late cleanup of redundant definitions."Jonas Paulsson
2022-12-01[CodeGen] Add new pass for late cleanup of redundant definitions.Jonas Paulsson
2022-07-16Revert rG14364200821f7b2d97edf6e78160c514800d3ec6 "[ARM] Regenerate reg_seque...Simon Pilgrim
2022-07-16[ARM] Regenerate reg_sequence.ll test checksSimon Pilgrim
2020-08-27[ARM] Make MachineVerifier more strict about terminatorsSam Parker
2019-04-17[ARM] tighten test checks; NFCSanjay Patel
2019-04-17[ARM] make test checks more thorough; NFCSanjay Patel
2019-04-03[DAGCombiner] loosen restrictions for moving shuffles after vector binopSanjay Patel
2018-05-17[ARM] preserve test intent by removing undefSanjay Patel
2018-05-16[ARM] preserve test intent by removing undefSanjay Patel
2015-09-30[ARM][NEON] Use address space in vld([1234]|[234]lane) and vst([1234]|[234]la...Jeroen Ketema
2015-02-27[opaque pointer type] Add textual IR support for explicit type parameter to l...David Blaikie
2015-02-27[opaque pointer type] Add textual IR support for explicit type parameter to g...David Blaikie
2014-05-30ARM & AArch64: make use of common cmpxchg idioms after expansionTim Northover
2014-02-10ARM: use LLVM IR to represent the vshrn operationTim Northover
2013-10-11Revert "Tests: Be less dependent on a specific schedule/regalloc"Matthias Braun
2013-10-11Tests: Be less dependent on a specific schedule/regallocMatthias Braun
2013-08-20ARM: implement some simple f64 materializations.Tim Northover
2013-07-14Mass update to CodeGen tests to use CHECK-LABEL for labels corresponding to f...Stephen Lin
2013-02-22Make ARMAsmPrinter generate the correct alignment specifier syntax in instruc...Kristof Beyls
2012-09-27Enable the new coalescer algorithm by default.Jakob Stoklund Olesen
2012-09-20Try to make these tests more portable.Evan Cheng
2012-09-18Use vld1 / vst2 for unaligned v2f64 load / store. e.g. Use vld1.16 for 2-byteEvan Cheng
2012-04-01This commit contains a few changes that had to go in together.Nadav Rotem
2011-11-14ARM VLDR/VSTR instructions don't need a size suffix.Jim Grosbach
2011-11-07Simplify some uses of utohexstr.Benjamin Kramer
2011-07-15Remove VMOVDneon and VMOVQ, which are just aliases for VORR. This continues ...Owen Anderson
2011-03-31Fix ARM tests to be register allocator independent.Jakob Stoklund Olesen
2010-12-05Making use of VFP / NEON floating point multiply-accumulate / subtraction isEvan Cheng
2010-11-03Two sets of changes. Sorry they are intermingled.Evan Cheng
2010-10-21putback r116983 and fix simple-fp-encoding.ll testsAndrew Trick
2010-10-21Revert r116983, which is breaking all the buildbots.Owen Anderson
2010-10-21Add missing scheduling itineraries for transfers between core registers and V...Evan Cheng
2010-10-09Correct some load / store instruction itinerary mistakes:Evan Cheng
2010-10-08Change register allocation order for ARM VFP and NEON registers to put theBob Wilson
2010-09-02Convert VLD1 and VLD2 instructions to use pseudo-instructions untilBob Wilson
2010-08-27Add alignment arguments to all the NEON load/store intrinsics.Bob Wilson
2010-08-20Replace some NEON vmovl intrinsic that I missed earlier.Bob Wilson
2010-07-13Use a target-specific VMOVIMM DAG node instead of BUILD_VECTOR to representBob Wilson
2010-07-09Print "dregpair" NEON operands with a space between them, for readability andBob Wilson
2010-07-09Reenable DAG combining for vector shuffles. It looks like it was temporarilyBob Wilson
2010-06-24Eliminate the other half of the BRCOND optimization, and updateDan Gohman
2010-06-17Remove arm_apcscc from the test files. It is the default and doing thisRafael Espindola
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