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AgeCommit message (Expand)Author
2025-11-23Revert "[RegAlloc] Fix the terminal rule check for interfere with DstReg (#16...Aiden Grossman
2025-11-23[RegAlloc] Fix the terminal rule check for interfere with DstReg (#168661)hstk30-hw
2025-11-20[LLVM][CodeGen][SVE] Only use unpredicated bfloat instructions when all lanes...Paul Walker
2025-11-20[AArch64][SVE] Implement demanded bits for @llvm.aarch64.sve.cntp (#168714)Benjamin Maxwell
2025-11-19DAG: Use poison for some vector result widening (#168290)Matt Arsenault
2025-11-19[AArch64][GlobalISel] Added support for hadd family of intrinsics (#163985)Joshua Rodriguez
2025-11-19[AArch64] match TRN starting from undef elements (#167955)Philip Ginsbach-Chen
2025-11-19[AArch64][GlobalISel] Check unmergeSrc is a vector in matchCombineBuildUnmerg...Ryan Cowan
2025-11-18[AArch64] Reorder Comparison Trees to Facilitate CSE (#168064)Marius Kamp
2025-11-18[AArch64][GISel] Don't crash in known-bits when copying from vectors to non-v...Nathan Corbyn
2025-11-18[CGP]: Optimize mul.overflow. (#148343)Hassnaa Hamdi
2025-11-18[LLVM][CodeGen][SVE] Use DUPM for constantfp splats. (#168391)Paul Walker
2025-11-18[AArch64][GlobalISel] Add better basic legalization for llround. (#168427)David Green
2025-11-18[DAGCombiner] Fold select into partial.reduce.add operands. (#167857)Sander de Smalen
2025-11-18[AArch64][SME] Add support for zeroing ZT0 to CommitZASavePseudo (#166360)Benjamin Maxwell
2025-11-17[Arm64EC] Preserve X9 for indirect calls. (#167782)Eli Friedman
2025-11-18[AArch64] Treat COPY between cross-register banks as expensive (#167661)Guy David
2025-11-17[AArch64][GlobalISel] Add basic GISel test coverage for lround and llround. NFCDavid Green
2025-11-17[AArch64] Optimize extending loads of small vectors (#163064)Guy David
2025-11-17[AArch64][GlobalISel] Add combine for build_vector(unmerge, unmerge, undef, u...Ryan Cowan
2025-11-17[DAG] Add strictfp implicit def reg after metadata. (#168282)David Green
2025-11-17[AArch64][GlobalISel] Fix vecreduce(zext) fold from illegal types. (#167944)David Green
2025-11-17[GlobalMerge]Prefer use global-merge-max-offset instead of the target-specifi...hstk30-hw
2025-11-16[DAG] Add baseline test coverage for #161036 (#168278)Simon Pilgrim
2025-11-16[AArch64][test] Improve pr166870.ll test case (#168194)Alex Bradbury
2025-11-15[SelectionDAG] Fix AArch64 machine verifier bug when expanding LOOP_DEPENDENC...AZero13
2025-11-14[AArch64][GlobalISel] Improve lowering of vector fp16 fpext (#165554)Ryan Cowan
2025-11-14[AArch64][FEAT_CMPBR] Codegen for Armv9.6-a CBB and CBH (#164899)David Tellenbach
2025-11-14[AArch64][DebugInfo]Add Target hooks for InstrRef on AArch64 (#165953)Shubham Sandeep Rastogi
2025-11-14[AArch64] Remove FEAT_TME assembly and ACLE support (#167687)Jonathan Thackray
2025-11-14[AArch64][SME] Handle SME state around TLS-descriptor calls (#155608)Benjamin Maxwell
2025-11-14[GlobalISel] Add support for value/constants as inline asm memory operand (#1...Pierre van Houtryve
2025-11-13[AArch64] Make the list of outline atomic supported operations explicit (#167...David Green
2025-11-13[AArch64][SVE] Allow basic use of `target("aarch64.svcount")` with +sve (#16...Benjamin Maxwell
2025-11-13[AArch64] Generalize CSEL a, b, cc, SUBS(SUB(x,y), 0) -> CSEL a, b, cc, SUBS...AZero13
2025-11-13[AArch64] Use SVE fdot for partial.reduce.fadd for NEON types. (#167856)Sander de Smalen
2025-11-13Revert "[DAG] Fold (umin (sub a b) a) -> (usubo a b); (select usubo.1 a usubo...Simon Pilgrim
2025-11-12DAG: Use poison when widening build_vector (#167631)Matt Arsenault
2025-11-12DAG: exp opcodes cannotBeOrderedNegativeFP (#167604)Matt Arsenault
2025-11-12AArch64: Add baseline test for treating exp as known positive (#167603)Matt Arsenault
2025-11-12[DAG] Fold (umin (sub a b) a) -> (usubo a b); (select usubo.1 a usubo.0) (#16...Chaitanya Koparkar
2025-11-12[AArch64] Add 'REQUIRES: asserts' to regalloc-hint-movprfx.mirSander de Smalen
2025-11-12[LLVM][CodeGen][SVE] Use BFMLALB for promoted bfloat fma operations. (#167340)Paul Walker
2025-11-12[AArch64][SME] Enable split SVE for hazard padding in SVE CC functions (#166561)Benjamin Maxwell
2025-11-12[AArch64] Prioritize regalloc hints over movprfx hints (#167480)Sander de Smalen
2025-11-11AArch64: align pair-wise spills on WoS to 16-byte (#166902)Saleem Abdulrasool
2025-11-11[MachineCopyPropagation] Remove logic to recognise and delete no-op moves pro...Alex Bradbury
2025-11-11AArch64: Convert tests to opaque pointers (#167442)Matt Arsenault
2025-11-11MachineCombiner: Partially fix losing subregister indexes (#141661)Matt Arsenault
2025-11-10[AArch64] Allow peephole to optimize AND + signed compare with 0 (#153608)AZero13