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path: root/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
AgeCommit message (Expand)Author
2025-11-22[AMDGPU] Enable serializing of allocated preload kernarg SGPRs info (#168374)tyb0807
2025-11-19[AMDGPU] Ignore wavefront barrier latency during scheduling DAG mutation (#16...Carl Ritson
2025-11-17[AMDGPU] Add amdgpu-lower-exec-sync pass to lower named-barrier globals (#165...Chaitanya
2025-11-02[ADT] Prepare to deprecate variadic `StringSwitch::Cases`. NFC. (#166020)Jakub Kuderski
2025-10-30[AMDGPU] Enable "amdgpu-uniform-intrinsic-combine" pass in pipeline. (#162819)Pankaj Dwivedi
2025-10-29[AMDGPU] make AMDGPUUniformIntrinsicCombine a function pass (#165265)Pankaj Dwivedi
2025-10-25[llvm] Make getEffectiveRelocModel helper consistent across targets. NFC (#16...Sam Clegg
2025-10-23[Passes] Report error when pass requires target machine (#142550)paperchalice
2025-10-21[AMDGPU] Add DAG mutation to improve scheduling before barriers (#142716)Carl Ritson
2025-10-09[AMDGPU] Introduce "amdgpu-uniform-intrinsic-combine" pass to combine uniform...Pankaj Dwivedi
2025-10-08[AMDGPU] Add the missing enabling check of AMDGPUAttributor (#162420)Shilei Tian
2025-10-08AMDGPU: skip AMDGPUAttributor pass on R600 some more. (#162418)James Y Knight
2025-10-07AMDGPU: skip AMDGPUAttributor and AMDGPUImageIntrinsicOptimizerPass on R600. ...James Y Knight
2025-10-01[AMDGPU] Move LowerBufferFatPointers after LoadStoreVectorizer and remove the...Gang Chen
2025-09-11[llvm] Move data layout string computation to TargetParser (#157612)Reid Kleckner
2025-09-05[AMDGPU] Register amdgpu-lower-vgpr-encoding pass in npm (#156971)Stanislav Mekhanoshin
2025-09-04[AMDGPU] High VGPR lowering on gfx1250 (#156965)Stanislav Mekhanoshin
2025-08-28AMDGPU: Refactor lowering of s_barrier to split barriers (#154648)Nicolai Hähnle
2025-08-22[AMDGPU][NFC] Only include CodeGenPassBuilder.h where needed. (#154769)Ivan Kosarev
2025-08-14[AMDGPU] Delete AMDGPU Unify Metadata pass (#153548)Shoreshen
2025-07-30Reapply "[CodeGen][NPM] Stitch up loop passes in codegen pipeline" (#151098)Vikram Hegde
2025-07-28[HIPSTDPAR] Add handling for math builtins (#140158)Alex Voicu
2025-07-28Revert "[CodeGen][NPM] Stitch up loop passes in codegen pipeline" (#150883)Vikram Hegde
2025-07-28[CodeGen][NPM] Stitch up loop passes in codegen pipeline (#148114)Vikram Hegde
2025-07-18AMDGPU: Add pass to replace constant materialize with AV pseudos (#149292)Matt Arsenault
2025-07-17[AMDGPU][NPM] Fill in addPreSched2 passes (#148112)Vikram Hegde
2025-07-10[AMDGPU][NewPM] Port "AMDGPUResourceUsageAnalysis" to NPM (#130959)Vikram Hegde
2025-07-09[CodeGen][NPM] Differentiate pipeline-required and opt-required passes (#135752)Akshat Oke
2025-07-09[AMDGPU][NPM] Complete optimized regalloc pipeline (#138491)Akshat Oke
2025-07-09[CodeGen][NPM] Support CodeGenSCCOrder in pipeline (#136818)Akshat Oke
2025-06-27AMDGPU: Introduce a pass to replace VGPR MFMAs with AGPR (#145024)Matt Arsenault
2025-06-23AMDGPU: Remove legacy pass manager version of AMDGPUAttributor (#145262)Matt Arsenault
2025-06-22AMDGPU: Use reportFatalUsageError for regalloc flag error (#145198)Matt Arsenault
2025-06-21AMDGPU: Really delete AMDGPUAnnotateKernelFeatures (#145136)Matt Arsenault
2025-06-20AMDGPU: Remove legacy pass manager version of AMDGPUUnifyMetadata (#144985)Matt Arsenault
2025-06-20AMDGPU: Remove legacy PM version of AMDGPUPromoteAllocaToVector (#144986)Matt Arsenault
2025-06-17[llvm] annotate interfaces in llvm/Target for DLL export (#143615)Andrew Rogers
2025-06-05[AMDGPU] Remove duplicated/confusing helpers. NFCI (#142598)Diana Picus
2025-06-03[MISched] Add templates for creating custom schedulers (#141935)Pengcheng Wang
2025-05-30Reapply "Reapply "[AMDGPU] Make `getAssumedAddrSpace` return AS1 for pointer ...Shilei Tian
2025-05-30Revert "Reapply "[AMDGPU] Make `getAssumedAddrSpace` return AS1 for pointer k...Shilei Tian
2025-05-30Reapply "[AMDGPU] Make `getAssumedAddrSpace` return AS1 for pointer kernel ar...Shilei Tian
2025-05-30Revert "[AMDGPU] Make `getAssumedAddrSpace` return AS1 for pointer kernel arg...Shilei Tian
2025-05-30[AMDGPU] Make `getAssumedAddrSpace` return AS1 for pointer kernel arguments (...Shilei Tian
2025-05-29[AMDGPU] Move InferAddressSpacesPass to middle end optimization pipeline (#13...Shilei Tian
2025-05-26[AMDGPU] Cluster export instructions in PostRA Scheduler (#141399)Carl Ritson
2025-05-19[AMDGPU] Set AS8 address width to 48 bitsAlexander Richardson
2025-05-11[AMDGPU] Move kernarg preload logic to separate pass (#130434)Austin Kerbow
2025-05-06Register assembly printer passes (#138348)Matthias Braun
2025-05-02[AMDGPU][Attributor] Add `ThinOrFullLTOPhase` as an argument (#123994)Shilei Tian
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