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| author | Vikram Hegde <115221833+vikramRH@users.noreply.github.com> | 2025-07-17 12:26:27 +0530 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2025-07-17 12:26:27 +0530 |
| commit | 72c61a6a255cd07c449f213bef9439ab0ee85c08 (patch) | |
| tree | 3389f2f3554f666e2972fc5e2819d2aec941b844 /llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp | |
| parent | 4a3cb437a32f5611b909fe7e067a9a9d28c2b845 (diff) | |
[AMDGPU][NPM] Fill in addPreSched2 passes (#148112)
same as https://github.com/llvm/llvm-project/pull/139516
Co-authored-by : Oke, Akshat
<[Akshat.Oke@amd.com](mailto:Akshat.Oke@amd.com)>
Diffstat (limited to 'llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp')
| -rw-r--r-- | llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp index f4dc4a483181..31a80e00edd3 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp @@ -2284,6 +2284,12 @@ void AMDGPUCodeGenPassBuilder::addPostRegAlloc(AddMachinePass &addPass) const { Base::addPostRegAlloc(addPass); } +void AMDGPUCodeGenPassBuilder::addPreSched2(AddMachinePass &addPass) const { + if (TM.getOptLevel() > CodeGenOptLevel::None) + addPass(SIShrinkInstructionsPass()); + addPass(SIPostRABundlerPass()); +} + void AMDGPUCodeGenPassBuilder::addPreEmitPass(AddMachinePass &addPass) const { if (isPassEnabled(EnableVOPD, CodeGenOptLevel::Less)) { addPass(GCNCreateVOPDPass()); |