diff options
Diffstat (limited to 'llvm/test/CodeGen/AMDGPU/atomic_optimizations_raw_buffer.ll')
| -rw-r--r-- | llvm/test/CodeGen/AMDGPU/atomic_optimizations_raw_buffer.ll | 1206 |
1 files changed, 652 insertions, 554 deletions
diff --git a/llvm/test/CodeGen/AMDGPU/atomic_optimizations_raw_buffer.ll b/llvm/test/CodeGen/AMDGPU/atomic_optimizations_raw_buffer.ll index ca94d68f0191..995d3fee6729 100644 --- a/llvm/test/CodeGen/AMDGPU/atomic_optimizations_raw_buffer.ll +++ b/llvm/test/CodeGen/AMDGPU/atomic_optimizations_raw_buffer.ll @@ -23,18 +23,18 @@ define amdgpu_kernel void @add_i32_constant(ptr addrspace(1) %out, ptr addrspace ; GFX6-NEXT: v_mbcnt_hi_u32_b32_e32 v0, s5, v0 ; GFX6-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 ; GFX6-NEXT: ; implicit-def: $vgpr1 -; GFX6-NEXT: s_and_saveexec_b64 s[2:3], vcc +; GFX6-NEXT: s_and_saveexec_b64 s[0:1], vcc ; GFX6-NEXT: s_cbranch_execz .LBB0_2 ; GFX6-NEXT: ; %bb.1: -; GFX6-NEXT: s_load_dwordx4 s[8:11], s[0:1], 0xd +; GFX6-NEXT: s_load_dwordx4 s[8:11], s[2:3], 0xd ; GFX6-NEXT: s_bcnt1_i32_b64 s4, s[4:5] ; GFX6-NEXT: s_mul_i32 s4, s4, 5 ; GFX6-NEXT: v_mov_b32_e32 v1, s4 ; GFX6-NEXT: s_waitcnt lgkmcnt(0) ; GFX6-NEXT: buffer_atomic_add v1, off, s[8:11], 0 glc ; GFX6-NEXT: .LBB0_2: -; GFX6-NEXT: s_or_b64 exec, exec, s[2:3] -; GFX6-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9 +; GFX6-NEXT: s_or_b64 exec, exec, s[0:1] +; GFX6-NEXT: s_load_dwordx2 s[0:1], s[2:3], 0x9 ; GFX6-NEXT: s_mov_b32 s3, 0xf000 ; GFX6-NEXT: s_mov_b32 s2, -1 ; GFX6-NEXT: s_waitcnt vmcnt(0) @@ -51,18 +51,18 @@ define amdgpu_kernel void @add_i32_constant(ptr addrspace(1) %out, ptr addrspace ; GFX8-NEXT: v_mbcnt_hi_u32_b32 v0, s5, v0 ; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 ; GFX8-NEXT: ; implicit-def: $vgpr1 -; GFX8-NEXT: s_and_saveexec_b64 s[2:3], vcc +; GFX8-NEXT: s_and_saveexec_b64 s[0:1], vcc ; GFX8-NEXT: s_cbranch_execz .LBB0_2 ; GFX8-NEXT: ; %bb.1: -; GFX8-NEXT: s_load_dwordx4 s[8:11], s[0:1], 0x34 +; GFX8-NEXT: s_load_dwordx4 s[8:11], s[2:3], 0x34 ; GFX8-NEXT: s_bcnt1_i32_b64 s4, s[4:5] ; GFX8-NEXT: s_mul_i32 s4, s4, 5 ; GFX8-NEXT: v_mov_b32_e32 v1, s4 ; GFX8-NEXT: s_waitcnt lgkmcnt(0) ; GFX8-NEXT: buffer_atomic_add v1, off, s[8:11], 0 glc ; GFX8-NEXT: .LBB0_2: -; GFX8-NEXT: s_or_b64 exec, exec, s[2:3] -; GFX8-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 +; GFX8-NEXT: s_or_b64 exec, exec, s[0:1] +; GFX8-NEXT: s_load_dwordx2 s[0:1], s[2:3], 0x24 ; GFX8-NEXT: s_waitcnt vmcnt(0) ; GFX8-NEXT: v_readfirstlane_b32 s2, v1 ; GFX8-NEXT: v_mad_u32_u24 v2, v0, 5, s2 @@ -79,18 +79,18 @@ define amdgpu_kernel void @add_i32_constant(ptr addrspace(1) %out, ptr addrspace ; GFX9-NEXT: v_mbcnt_hi_u32_b32 v0, s5, v0 ; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 ; GFX9-NEXT: ; implicit-def: $vgpr1 -; GFX9-NEXT: s_and_saveexec_b64 s[2:3], vcc +; GFX9-NEXT: s_and_saveexec_b64 s[0:1], vcc ; GFX9-NEXT: s_cbranch_execz .LBB0_2 ; GFX9-NEXT: ; %bb.1: -; GFX9-NEXT: s_load_dwordx4 s[8:11], s[0:1], 0x34 +; GFX9-NEXT: s_load_dwordx4 s[8:11], s[2:3], 0x34 ; GFX9-NEXT: s_bcnt1_i32_b64 s4, s[4:5] ; GFX9-NEXT: s_mul_i32 s4, s4, 5 ; GFX9-NEXT: v_mov_b32_e32 v1, s4 ; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: buffer_atomic_add v1, off, s[8:11], 0 glc ; GFX9-NEXT: .LBB0_2: -; GFX9-NEXT: s_or_b64 exec, exec, s[2:3] -; GFX9-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 +; GFX9-NEXT: s_or_b64 exec, exec, s[0:1] +; GFX9-NEXT: s_load_dwordx2 s[0:1], s[2:3], 0x24 ; GFX9-NEXT: s_waitcnt vmcnt(0) ; GFX9-NEXT: v_readfirstlane_b32 s2, v1 ; GFX9-NEXT: v_mov_b32_e32 v2, 0 @@ -106,10 +106,10 @@ define amdgpu_kernel void @add_i32_constant(ptr addrspace(1) %out, ptr addrspace ; GFX10W64-NEXT: v_mbcnt_lo_u32_b32 v0, s4, 0 ; GFX10W64-NEXT: v_mbcnt_hi_u32_b32 v0, s5, v0 ; GFX10W64-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 -; GFX10W64-NEXT: s_and_saveexec_b64 s[2:3], vcc +; GFX10W64-NEXT: s_and_saveexec_b64 s[0:1], vcc ; GFX10W64-NEXT: s_cbranch_execz .LBB0_2 ; GFX10W64-NEXT: ; %bb.1: -; GFX10W64-NEXT: s_load_dwordx4 s[8:11], s[0:1], 0x34 +; GFX10W64-NEXT: s_load_dwordx4 s[8:11], s[2:3], 0x34 ; GFX10W64-NEXT: s_bcnt1_i32_b64 s4, s[4:5] ; GFX10W64-NEXT: s_mul_i32 s4, s4, 5 ; GFX10W64-NEXT: v_mov_b32_e32 v1, s4 @@ -117,9 +117,10 @@ define amdgpu_kernel void @add_i32_constant(ptr addrspace(1) %out, ptr addrspace ; GFX10W64-NEXT: buffer_atomic_add v1, off, s[8:11], 0 glc ; GFX10W64-NEXT: .LBB0_2: ; GFX10W64-NEXT: s_waitcnt_depctr 0xffe3 -; GFX10W64-NEXT: s_or_b64 exec, exec, s[2:3] -; GFX10W64-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 +; GFX10W64-NEXT: s_or_b64 exec, exec, s[0:1] +; GFX10W64-NEXT: s_load_dwordx2 s[0:1], s[2:3], 0x24 ; GFX10W64-NEXT: s_waitcnt vmcnt(0) +; GFX10W64-NEXT: s_mov_b32 null, 0 ; GFX10W64-NEXT: v_readfirstlane_b32 s2, v1 ; GFX10W64-NEXT: v_mov_b32_e32 v1, 0 ; GFX10W64-NEXT: v_mad_u32_u24 v0, v0, 5, s2 @@ -129,24 +130,25 @@ define amdgpu_kernel void @add_i32_constant(ptr addrspace(1) %out, ptr addrspace ; ; GFX10W32-LABEL: add_i32_constant: ; GFX10W32: ; %bb.0: ; %entry -; GFX10W32-NEXT: s_mov_b32 s3, exec_lo +; GFX10W32-NEXT: s_mov_b32 s1, exec_lo ; GFX10W32-NEXT: ; implicit-def: $vgpr1 -; GFX10W32-NEXT: v_mbcnt_lo_u32_b32 v0, s3, 0 +; GFX10W32-NEXT: v_mbcnt_lo_u32_b32 v0, s1, 0 ; GFX10W32-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 -; GFX10W32-NEXT: s_and_saveexec_b32 s2, vcc_lo +; GFX10W32-NEXT: s_and_saveexec_b32 s0, vcc_lo ; GFX10W32-NEXT: s_cbranch_execz .LBB0_2 ; GFX10W32-NEXT: ; %bb.1: -; GFX10W32-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x34 -; GFX10W32-NEXT: s_bcnt1_i32_b32 s3, s3 -; GFX10W32-NEXT: s_mul_i32 s3, s3, 5 -; GFX10W32-NEXT: v_mov_b32_e32 v1, s3 +; GFX10W32-NEXT: s_load_dwordx4 s[4:7], s[2:3], 0x34 +; GFX10W32-NEXT: s_bcnt1_i32_b32 s1, s1 +; GFX10W32-NEXT: s_mul_i32 s1, s1, 5 +; GFX10W32-NEXT: v_mov_b32_e32 v1, s1 ; GFX10W32-NEXT: s_waitcnt lgkmcnt(0) ; GFX10W32-NEXT: buffer_atomic_add v1, off, s[4:7], 0 glc ; GFX10W32-NEXT: .LBB0_2: ; GFX10W32-NEXT: s_waitcnt_depctr 0xffe3 -; GFX10W32-NEXT: s_or_b32 exec_lo, exec_lo, s2 -; GFX10W32-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 +; GFX10W32-NEXT: s_or_b32 exec_lo, exec_lo, s0 +; GFX10W32-NEXT: s_load_dwordx2 s[0:1], s[2:3], 0x24 ; GFX10W32-NEXT: s_waitcnt vmcnt(0) +; GFX10W32-NEXT: s_mov_b32 null, 0 ; GFX10W32-NEXT: v_readfirstlane_b32 s2, v1 ; GFX10W32-NEXT: v_mov_b32_e32 v1, 0 ; GFX10W32-NEXT: v_mad_u32_u24 v0, v0, 5, s2 @@ -157,7 +159,7 @@ define amdgpu_kernel void @add_i32_constant(ptr addrspace(1) %out, ptr addrspace ; GFX11W64-LABEL: add_i32_constant: ; GFX11W64: ; %bb.0: ; %entry ; GFX11W64-NEXT: s_mov_b64 s[4:5], exec -; GFX11W64-NEXT: s_mov_b64 s[2:3], exec +; GFX11W64-NEXT: s_mov_b64 s[0:1], exec ; GFX11W64-NEXT: v_mbcnt_lo_u32_b32 v0, s4, 0 ; GFX11W64-NEXT: ; implicit-def: $vgpr1 ; GFX11W64-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) @@ -165,7 +167,7 @@ define amdgpu_kernel void @add_i32_constant(ptr addrspace(1) %out, ptr addrspace ; GFX11W64-NEXT: v_cmpx_eq_u32_e32 0, v0 ; GFX11W64-NEXT: s_cbranch_execz .LBB0_2 ; GFX11W64-NEXT: ; %bb.1: -; GFX11W64-NEXT: s_load_b128 s[8:11], s[0:1], 0x34 +; GFX11W64-NEXT: s_load_b128 s[8:11], s[2:3], 0x34 ; GFX11W64-NEXT: s_bcnt1_i32_b64 s4, s[4:5] ; GFX11W64-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) ; GFX11W64-NEXT: s_mul_i32 s4, s4, 5 @@ -173,8 +175,8 @@ define amdgpu_kernel void @add_i32_constant(ptr addrspace(1) %out, ptr addrspace ; GFX11W64-NEXT: s_waitcnt lgkmcnt(0) ; GFX11W64-NEXT: buffer_atomic_add_u32 v1, off, s[8:11], 0 glc ; GFX11W64-NEXT: .LBB0_2: -; GFX11W64-NEXT: s_or_b64 exec, exec, s[2:3] -; GFX11W64-NEXT: s_load_b64 s[0:1], s[0:1], 0x24 +; GFX11W64-NEXT: s_or_b64 exec, exec, s[0:1] +; GFX11W64-NEXT: s_load_b64 s[0:1], s[2:3], 0x24 ; GFX11W64-NEXT: s_waitcnt vmcnt(0) ; GFX11W64-NEXT: v_readfirstlane_b32 s2, v1 ; GFX11W64-NEXT: v_mov_b32_e32 v1, 0 @@ -188,24 +190,24 @@ define amdgpu_kernel void @add_i32_constant(ptr addrspace(1) %out, ptr addrspace ; ; GFX11W32-LABEL: add_i32_constant: ; GFX11W32: ; %bb.0: ; %entry -; GFX11W32-NEXT: s_mov_b32 s3, exec_lo -; GFX11W32-NEXT: s_mov_b32 s2, exec_lo -; GFX11W32-NEXT: v_mbcnt_lo_u32_b32 v0, s3, 0 +; GFX11W32-NEXT: s_mov_b32 s1, exec_lo +; GFX11W32-NEXT: s_mov_b32 s0, exec_lo +; GFX11W32-NEXT: v_mbcnt_lo_u32_b32 v0, s1, 0 ; GFX11W32-NEXT: ; implicit-def: $vgpr1 ; GFX11W32-NEXT: s_delay_alu instid0(VALU_DEP_1) ; GFX11W32-NEXT: v_cmpx_eq_u32_e32 0, v0 ; GFX11W32-NEXT: s_cbranch_execz .LBB0_2 ; GFX11W32-NEXT: ; %bb.1: -; GFX11W32-NEXT: s_load_b128 s[4:7], s[0:1], 0x34 -; GFX11W32-NEXT: s_bcnt1_i32_b32 s3, s3 +; GFX11W32-NEXT: s_load_b128 s[4:7], s[2:3], 0x34 +; GFX11W32-NEXT: s_bcnt1_i32_b32 s1, s1 ; GFX11W32-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) -; GFX11W32-NEXT: s_mul_i32 s3, s3, 5 -; GFX11W32-NEXT: v_mov_b32_e32 v1, s3 +; GFX11W32-NEXT: s_mul_i32 s1, s1, 5 +; GFX11W32-NEXT: v_mov_b32_e32 v1, s1 ; GFX11W32-NEXT: s_waitcnt lgkmcnt(0) ; GFX11W32-NEXT: buffer_atomic_add_u32 v1, off, s[4:7], 0 glc ; GFX11W32-NEXT: .LBB0_2: -; GFX11W32-NEXT: s_or_b32 exec_lo, exec_lo, s2 -; GFX11W32-NEXT: s_load_b64 s[0:1], s[0:1], 0x24 +; GFX11W32-NEXT: s_or_b32 exec_lo, exec_lo, s0 +; GFX11W32-NEXT: s_load_b64 s[0:1], s[2:3], 0x24 ; GFX11W32-NEXT: s_waitcnt vmcnt(0) ; GFX11W32-NEXT: v_readfirstlane_b32 s2, v1 ; GFX11W32-NEXT: v_mov_b32_e32 v1, 0 @@ -220,7 +222,7 @@ define amdgpu_kernel void @add_i32_constant(ptr addrspace(1) %out, ptr addrspace ; GFX12W64-LABEL: add_i32_constant: ; GFX12W64: ; %bb.0: ; %entry ; GFX12W64-NEXT: s_mov_b64 s[4:5], exec -; GFX12W64-NEXT: s_mov_b64 s[2:3], exec +; GFX12W64-NEXT: s_mov_b64 s[0:1], exec ; GFX12W64-NEXT: v_mbcnt_lo_u32_b32 v0, s4, 0 ; GFX12W64-NEXT: ; implicit-def: $vgpr1 ; GFX12W64-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) @@ -228,7 +230,7 @@ define amdgpu_kernel void @add_i32_constant(ptr addrspace(1) %out, ptr addrspace ; GFX12W64-NEXT: v_cmpx_eq_u32_e32 0, v0 ; GFX12W64-NEXT: s_cbranch_execz .LBB0_2 ; GFX12W64-NEXT: ; %bb.1: -; GFX12W64-NEXT: s_load_b128 s[8:11], s[0:1], 0x34 +; GFX12W64-NEXT: s_load_b128 s[8:11], s[2:3], 0x34 ; GFX12W64-NEXT: s_bcnt1_i32_b64 s4, s[4:5] ; GFX12W64-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) ; GFX12W64-NEXT: s_mul_i32 s4, s4, 5 @@ -236,8 +238,8 @@ define amdgpu_kernel void @add_i32_constant(ptr addrspace(1) %out, ptr addrspace ; GFX12W64-NEXT: s_wait_kmcnt 0x0 ; GFX12W64-NEXT: buffer_atomic_add_u32 v1, off, s[8:11], null th:TH_ATOMIC_RETURN ; GFX12W64-NEXT: .LBB0_2: -; GFX12W64-NEXT: s_or_b64 exec, exec, s[2:3] -; GFX12W64-NEXT: s_load_b64 s[0:1], s[0:1], 0x24 +; GFX12W64-NEXT: s_or_b64 exec, exec, s[0:1] +; GFX12W64-NEXT: s_load_b64 s[0:1], s[2:3], 0x24 ; GFX12W64-NEXT: s_wait_loadcnt 0x0 ; GFX12W64-NEXT: v_readfirstlane_b32 s2, v1 ; GFX12W64-NEXT: v_mov_b32_e32 v1, 0 @@ -251,24 +253,24 @@ define amdgpu_kernel void @add_i32_constant(ptr addrspace(1) %out, ptr addrspace ; ; GFX12W32-LABEL: add_i32_constant: ; GFX12W32: ; %bb.0: ; %entry -; GFX12W32-NEXT: s_mov_b32 s3, exec_lo -; GFX12W32-NEXT: s_mov_b32 s2, exec_lo -; GFX12W32-NEXT: v_mbcnt_lo_u32_b32 v0, s3, 0 +; GFX12W32-NEXT: s_mov_b32 s1, exec_lo +; GFX12W32-NEXT: s_mov_b32 s0, exec_lo +; GFX12W32-NEXT: v_mbcnt_lo_u32_b32 v0, s1, 0 ; GFX12W32-NEXT: ; implicit-def: $vgpr1 ; GFX12W32-NEXT: s_delay_alu instid0(VALU_DEP_1) ; GFX12W32-NEXT: v_cmpx_eq_u32_e32 0, v0 ; GFX12W32-NEXT: s_cbranch_execz .LBB0_2 ; GFX12W32-NEXT: ; %bb.1: -; GFX12W32-NEXT: s_load_b128 s[4:7], s[0:1], 0x34 -; GFX12W32-NEXT: s_bcnt1_i32_b32 s3, s3 +; GFX12W32-NEXT: s_load_b128 s[4:7], s[2:3], 0x34 +; GFX12W32-NEXT: s_bcnt1_i32_b32 s1, s1 ; GFX12W32-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) -; GFX12W32-NEXT: s_mul_i32 s3, s3, 5 -; GFX12W32-NEXT: v_mov_b32_e32 v1, s3 +; GFX12W32-NEXT: s_mul_i32 s1, s1, 5 +; GFX12W32-NEXT: v_mov_b32_e32 v1, s1 ; GFX12W32-NEXT: s_wait_kmcnt 0x0 ; GFX12W32-NEXT: buffer_atomic_add_u32 v1, off, s[4:7], null th:TH_ATOMIC_RETURN ; GFX12W32-NEXT: .LBB0_2: -; GFX12W32-NEXT: s_or_b32 exec_lo, exec_lo, s2 -; GFX12W32-NEXT: s_load_b64 s[0:1], s[0:1], 0x24 +; GFX12W32-NEXT: s_or_b32 exec_lo, exec_lo, s0 +; GFX12W32-NEXT: s_load_b64 s[0:1], s[2:3], 0x24 ; GFX12W32-NEXT: s_wait_loadcnt 0x0 ; GFX12W32-NEXT: v_readfirstlane_b32 s2, v1 ; GFX12W32-NEXT: v_mov_b32_e32 v1, 0 @@ -289,23 +291,23 @@ define amdgpu_kernel void @add_i32_uniform(ptr addrspace(1) %out, ptr addrspace( ; GFX6-LABEL: add_i32_uniform: ; GFX6: ; %bb.0: ; %entry ; GFX6-NEXT: s_mov_b64 s[4:5], exec -; GFX6-NEXT: s_load_dword s6, s[0:1], 0x11 +; GFX6-NEXT: s_load_dword s6, s[2:3], 0x11 ; GFX6-NEXT: v_mbcnt_lo_u32_b32_e64 v0, s4, 0 ; GFX6-NEXT: v_mbcnt_hi_u32_b32_e32 v0, s5, v0 ; GFX6-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 ; GFX6-NEXT: ; implicit-def: $vgpr1 -; GFX6-NEXT: s_and_saveexec_b64 s[2:3], vcc +; GFX6-NEXT: s_and_saveexec_b64 s[0:1], vcc ; GFX6-NEXT: s_cbranch_execz .LBB1_2 ; GFX6-NEXT: ; %bb.1: -; GFX6-NEXT: s_load_dwordx4 s[8:11], s[0:1], 0xd +; GFX6-NEXT: s_load_dwordx4 s[8:11], s[2:3], 0xd ; GFX6-NEXT: s_bcnt1_i32_b64 s4, s[4:5] ; GFX6-NEXT: s_waitcnt lgkmcnt(0) ; GFX6-NEXT: s_mul_i32 s4, s6, s4 ; GFX6-NEXT: v_mov_b32_e32 v1, s4 ; GFX6-NEXT: buffer_atomic_add v1, off, s[8:11], 0 glc ; GFX6-NEXT: .LBB1_2: -; GFX6-NEXT: s_or_b64 exec, exec, s[2:3] -; GFX6-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9 +; GFX6-NEXT: s_or_b64 exec, exec, s[0:1] +; GFX6-NEXT: s_load_dwordx2 s[0:1], s[2:3], 0x9 ; GFX6-NEXT: s_mov_b32 s3, 0xf000 ; GFX6-NEXT: s_mov_b32 s2, -1 ; GFX6-NEXT: s_waitcnt vmcnt(0) @@ -318,24 +320,24 @@ define amdgpu_kernel void @add_i32_uniform(ptr addrspace(1) %out, ptr addrspace( ; ; GFX8-LABEL: add_i32_uniform: ; GFX8: ; %bb.0: ; %entry -; GFX8-NEXT: s_load_dword s6, s[0:1], 0x44 +; GFX8-NEXT: s_load_dword s6, s[2:3], 0x44 ; GFX8-NEXT: s_mov_b64 s[4:5], exec ; GFX8-NEXT: v_mbcnt_lo_u32_b32 v0, s4, 0 ; GFX8-NEXT: v_mbcnt_hi_u32_b32 v0, s5, v0 ; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 ; GFX8-NEXT: ; implicit-def: $vgpr1 -; GFX8-NEXT: s_and_saveexec_b64 s[2:3], vcc +; GFX8-NEXT: s_and_saveexec_b64 s[0:1], vcc ; GFX8-NEXT: s_cbranch_execz .LBB1_2 ; GFX8-NEXT: ; %bb.1: -; GFX8-NEXT: s_load_dwordx4 s[8:11], s[0:1], 0x34 +; GFX8-NEXT: s_load_dwordx4 s[8:11], s[2:3], 0x34 ; GFX8-NEXT: s_bcnt1_i32_b64 s4, s[4:5] ; GFX8-NEXT: s_waitcnt lgkmcnt(0) ; GFX8-NEXT: s_mul_i32 s4, s6, s4 ; GFX8-NEXT: v_mov_b32_e32 v1, s4 ; GFX8-NEXT: buffer_atomic_add v1, off, s[8:11], 0 glc ; GFX8-NEXT: .LBB1_2: -; GFX8-NEXT: s_or_b64 exec, exec, s[2:3] -; GFX8-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 +; GFX8-NEXT: s_or_b64 exec, exec, s[0:1] +; GFX8-NEXT: s_load_dwordx2 s[0:1], s[2:3], 0x24 ; GFX8-NEXT: s_waitcnt lgkmcnt(0) ; GFX8-NEXT: v_mul_lo_u32 v0, s6, v0 ; GFX8-NEXT: s_waitcnt vmcnt(0) @@ -348,24 +350,24 @@ define amdgpu_kernel void @add_i32_uniform(ptr addrspace(1) %out, ptr addrspace( ; ; GFX9-LABEL: add_i32_uniform: ; GFX9: ; %bb.0: ; %entry -; GFX9-NEXT: s_load_dword s6, s[0:1], 0x44 +; GFX9-NEXT: s_load_dword s6, s[2:3], 0x44 ; GFX9-NEXT: s_mov_b64 s[4:5], exec ; GFX9-NEXT: v_mbcnt_lo_u32_b32 v0, s4, 0 ; GFX9-NEXT: v_mbcnt_hi_u32_b32 v0, s5, v0 ; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 ; GFX9-NEXT: ; implicit-def: $vgpr1 -; GFX9-NEXT: s_and_saveexec_b64 s[2:3], vcc +; GFX9-NEXT: s_and_saveexec_b64 s[0:1], vcc ; GFX9-NEXT: s_cbranch_execz .LBB1_2 ; GFX9-NEXT: ; %bb.1: -; GFX9-NEXT: s_load_dwordx4 s[8:11], s[0:1], 0x34 +; GFX9-NEXT: s_load_dwordx4 s[8:11], s[2:3], 0x34 ; GFX9-NEXT: s_bcnt1_i32_b64 s4, s[4:5] ; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_mul_i32 s4, s6, s4 ; GFX9-NEXT: v_mov_b32_e32 v1, s4 ; GFX9-NEXT: buffer_atomic_add v1, off, s[8:11], 0 glc ; GFX9-NEXT: .LBB1_2: -; GFX9-NEXT: s_or_b64 exec, exec, s[2:3] -; GFX9-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 +; GFX9-NEXT: s_or_b64 exec, exec, s[0:1] +; GFX9-NEXT: s_load_dwordx2 s[0:1], s[2:3], 0x24 ; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: v_mul_lo_u32 v0, s6, v0 ; GFX9-NEXT: s_waitcnt vmcnt(0) @@ -377,16 +379,16 @@ define amdgpu_kernel void @add_i32_uniform(ptr addrspace(1) %out, ptr addrspace( ; ; GFX10W64-LABEL: add_i32_uniform: ; GFX10W64: ; %bb.0: ; %entry -; GFX10W64-NEXT: s_load_dword s6, s[0:1], 0x44 +; GFX10W64-NEXT: s_load_dword s6, s[2:3], 0x44 ; GFX10W64-NEXT: s_mov_b64 s[4:5], exec ; GFX10W64-NEXT: ; implicit-def: $vgpr1 ; GFX10W64-NEXT: v_mbcnt_lo_u32_b32 v0, s4, 0 ; GFX10W64-NEXT: v_mbcnt_hi_u32_b32 v0, s5, v0 ; GFX10W64-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 -; GFX10W64-NEXT: s_and_saveexec_b64 s[2:3], vcc +; GFX10W64-NEXT: s_and_saveexec_b64 s[0:1], vcc ; GFX10W64-NEXT: s_cbranch_execz .LBB1_2 ; GFX10W64-NEXT: ; %bb.1: -; GFX10W64-NEXT: s_load_dwordx4 s[8:11], s[0:1], 0x34 +; GFX10W64-NEXT: s_load_dwordx4 s[8:11], s[2:3], 0x34 ; GFX10W64-NEXT: s_bcnt1_i32_b64 s4, s[4:5] ; GFX10W64-NEXT: s_waitcnt lgkmcnt(0) ; GFX10W64-NEXT: s_mul_i32 s4, s6, s4 @@ -394,9 +396,10 @@ define amdgpu_kernel void @add_i32_uniform(ptr addrspace(1) %out, ptr addrspace( ; GFX10W64-NEXT: buffer_atomic_add v1, off, s[8:11], 0 glc ; GFX10W64-NEXT: .LBB1_2: ; GFX10W64-NEXT: s_waitcnt_depctr 0xffe3 -; GFX10W64-NEXT: s_or_b64 exec, exec, s[2:3] -; GFX10W64-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 +; GFX10W64-NEXT: s_or_b64 exec, exec, s[0:1] +; GFX10W64-NEXT: s_load_dwordx2 s[0:1], s[2:3], 0x24 ; GFX10W64-NEXT: s_waitcnt vmcnt(0) +; GFX10W64-NEXT: s_mov_b32 null, 0 ; GFX10W64-NEXT: v_readfirstlane_b32 s2, v1 ; GFX10W64-NEXT: s_waitcnt lgkmcnt(0) ; GFX10W64-NEXT: v_mad_u64_u32 v[0:1], s[2:3], s6, v0, s[2:3] @@ -406,37 +409,37 @@ define amdgpu_kernel void @add_i32_uniform(ptr addrspace(1) %out, ptr addrspace( ; ; GFX10W32-LABEL: add_i32_uniform: ; GFX10W32: ; %bb.0: ; %entry -; GFX10W32-NEXT: s_load_dword s2, s[0:1], 0x44 +; GFX10W32-NEXT: s_load_dword s0, s[2:3], 0x44 ; GFX10W32-NEXT: s_mov_b32 s4, exec_lo ; GFX10W32-NEXT: ; implicit-def: $vgpr1 ; GFX10W32-NEXT: v_mbcnt_lo_u32_b32 v0, s4, 0 ; GFX10W32-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 -; GFX10W32-NEXT: s_and_saveexec_b32 s3, vcc_lo +; GFX10W32-NEXT: s_and_saveexec_b32 s1, vcc_lo ; GFX10W32-NEXT: s_cbranch_execz .LBB1_2 ; GFX10W32-NEXT: ; %bb.1: -; GFX10W32-NEXT: s_load_dwordx4 s[8:11], s[0:1], 0x34 +; GFX10W32-NEXT: s_load_dwordx4 s[8:11], s[2:3], 0x34 ; GFX10W32-NEXT: s_bcnt1_i32_b32 s4, s4 ; GFX10W32-NEXT: s_waitcnt lgkmcnt(0) -; GFX10W32-NEXT: s_mul_i32 s4, s2, s4 +; GFX10W32-NEXT: s_mul_i32 s4, s0, s4 ; GFX10W32-NEXT: v_mov_b32_e32 v1, s4 ; GFX10W32-NEXT: buffer_atomic_add v1, off, s[8:11], 0 glc ; GFX10W32-NEXT: .LBB1_2: ; GFX10W32-NEXT: s_waitcnt_depctr 0xffe3 -; GFX10W32-NEXT: s_or_b32 exec_lo, exec_lo, s3 -; GFX10W32-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 +; GFX10W32-NEXT: s_or_b32 exec_lo, exec_lo, s1 +; GFX10W32-NEXT: s_load_dwordx2 s[2:3], s[2:3], 0x24 ; GFX10W32-NEXT: s_waitcnt vmcnt(0) ; GFX10W32-NEXT: v_readfirstlane_b32 s4, v1 ; GFX10W32-NEXT: s_waitcnt lgkmcnt(0) -; GFX10W32-NEXT: v_mad_u64_u32 v[0:1], s2, s2, v0, s[4:5] +; GFX10W32-NEXT: v_mad_u64_u32 v[0:1], s0, s0, v0, s[4:5] ; GFX10W32-NEXT: v_mov_b32_e32 v1, 0 -; GFX10W32-NEXT: global_store_dword v1, v0, s[0:1] +; GFX10W32-NEXT: global_store_dword v1, v0, s[2:3] ; GFX10W32-NEXT: s_endpgm ; ; GFX11W64-LABEL: add_i32_uniform: ; GFX11W64: ; %bb.0: ; %entry -; GFX11W64-NEXT: s_load_b32 s6, s[0:1], 0x44 +; GFX11W64-NEXT: s_load_b32 s6, s[2:3], 0x44 ; GFX11W64-NEXT: s_mov_b64 s[4:5], exec -; GFX11W64-NEXT: s_mov_b64 s[2:3], exec +; GFX11W64-NEXT: s_mov_b64 s[0:1], exec ; GFX11W64-NEXT: v_mbcnt_lo_u32_b32 v0, s4, 0 ; GFX11W64-NEXT: ; implicit-def: $vgpr1 ; GFX11W64-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) @@ -444,7 +447,7 @@ define amdgpu_kernel void @add_i32_uniform(ptr addrspace(1) %out, ptr addrspace( ; GFX11W64-NEXT: v_cmpx_eq_u32_e32 0, v0 ; GFX11W64-NEXT: s_cbranch_execz .LBB1_2 ; GFX11W64-NEXT: ; %bb.1: -; GFX11W64-NEXT: s_load_b128 s[8:11], s[0:1], 0x34 +; GFX11W64-NEXT: s_load_b128 s[8:11], s[2:3], 0x34 ; GFX11W64-NEXT: s_bcnt1_i32_b64 s4, s[4:5] ; GFX11W64-NEXT: s_waitcnt lgkmcnt(0) ; GFX11W64-NEXT: s_mul_i32 s4, s6, s4 @@ -452,8 +455,8 @@ define amdgpu_kernel void @add_i32_uniform(ptr addrspace(1) %out, ptr addrspace( ; GFX11W64-NEXT: v_mov_b32_e32 v1, s4 ; GFX11W64-NEXT: buffer_atomic_add_u32 v1, off, s[8:11], 0 glc ; GFX11W64-NEXT: .LBB1_2: -; GFX11W64-NEXT: s_or_b64 exec, exec, s[2:3] -; GFX11W64-NEXT: s_load_b64 s[0:1], s[0:1], 0x24 +; GFX11W64-NEXT: s_or_b64 exec, exec, s[0:1] +; GFX11W64-NEXT: s_load_b64 s[0:1], s[2:3], 0x24 ; GFX11W64-NEXT: s_waitcnt vmcnt(0) ; GFX11W64-NEXT: v_readfirstlane_b32 s2, v1 ; GFX11W64-NEXT: s_waitcnt lgkmcnt(0) @@ -467,41 +470,41 @@ define amdgpu_kernel void @add_i32_uniform(ptr addrspace(1) %out, ptr addrspace( ; ; GFX11W32-LABEL: add_i32_uniform: ; GFX11W32: ; %bb.0: ; %entry -; GFX11W32-NEXT: s_load_b32 s2, s[0:1], 0x44 +; GFX11W32-NEXT: s_load_b32 s0, s[2:3], 0x44 ; GFX11W32-NEXT: s_mov_b32 s4, exec_lo -; GFX11W32-NEXT: s_mov_b32 s3, exec_lo +; GFX11W32-NEXT: s_mov_b32 s1, exec_lo ; GFX11W32-NEXT: v_mbcnt_lo_u32_b32 v0, s4, 0 ; GFX11W32-NEXT: ; implicit-def: $vgpr1 ; GFX11W32-NEXT: s_delay_alu instid0(VALU_DEP_1) ; GFX11W32-NEXT: v_cmpx_eq_u32_e32 0, v0 ; GFX11W32-NEXT: s_cbranch_execz .LBB1_2 ; GFX11W32-NEXT: ; %bb.1: -; GFX11W32-NEXT: s_load_b128 s[8:11], s[0:1], 0x34 +; GFX11W32-NEXT: s_load_b128 s[8:11], s[2:3], 0x34 ; GFX11W32-NEXT: s_bcnt1_i32_b32 s4, s4 ; GFX11W32-NEXT: s_waitcnt lgkmcnt(0) -; GFX11W32-NEXT: s_mul_i32 s4, s2, s4 +; GFX11W32-NEXT: s_mul_i32 s4, s0, s4 ; GFX11W32-NEXT: s_delay_alu instid0(SALU_CYCLE_1) ; GFX11W32-NEXT: v_mov_b32_e32 v1, s4 ; GFX11W32-NEXT: buffer_atomic_add_u32 v1, off, s[8:11], 0 glc ; GFX11W32-NEXT: .LBB1_2: -; GFX11W32-NEXT: s_or_b32 exec_lo, exec_lo, s3 -; GFX11W32-NEXT: s_load_b64 s[0:1], s[0:1], 0x24 +; GFX11W32-NEXT: s_or_b32 exec_lo, exec_lo, s1 +; GFX11W32-NEXT: s_load_b64 s[2:3], s[2:3], 0x24 ; GFX11W32-NEXT: s_waitcnt vmcnt(0) ; GFX11W32-NEXT: v_readfirstlane_b32 s4, v1 ; GFX11W32-NEXT: s_waitcnt lgkmcnt(0) ; GFX11W32-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11W32-NEXT: v_mad_u64_u32 v[1:2], null, s2, v0, s[4:5] +; GFX11W32-NEXT: v_mad_u64_u32 v[1:2], null, s0, v0, s[4:5] ; GFX11W32-NEXT: v_mov_b32_e32 v0, 0 -; GFX11W32-NEXT: global_store_b32 v0, v1, s[0:1] +; GFX11W32-NEXT: global_store_b32 v0, v1, s[2:3] ; GFX11W32-NEXT: s_nop 0 ; GFX11W32-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) ; GFX11W32-NEXT: s_endpgm ; ; GFX12W64-LABEL: add_i32_uniform: ; GFX12W64: ; %bb.0: ; %entry -; GFX12W64-NEXT: s_load_b32 s6, s[0:1], 0x44 +; GFX12W64-NEXT: s_load_b32 s6, s[2:3], 0x44 ; GFX12W64-NEXT: s_mov_b64 s[4:5], exec -; GFX12W64-NEXT: s_mov_b64 s[2:3], exec +; GFX12W64-NEXT: s_mov_b64 s[0:1], exec ; GFX12W64-NEXT: v_mbcnt_lo_u32_b32 v0, s4, 0 ; GFX12W64-NEXT: ; implicit-def: $vgpr1 ; GFX12W64-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) @@ -509,7 +512,7 @@ define amdgpu_kernel void @add_i32_uniform(ptr addrspace(1) %out, ptr addrspace( ; GFX12W64-NEXT: v_cmpx_eq_u32_e32 0, v0 ; GFX12W64-NEXT: s_cbranch_execz .LBB1_2 ; GFX12W64-NEXT: ; %bb.1: -; GFX12W64-NEXT: s_load_b128 s[8:11], s[0:1], 0x34 +; GFX12W64-NEXT: s_load_b128 s[8:11], s[2:3], 0x34 ; GFX12W64-NEXT: s_bcnt1_i32_b64 s4, s[4:5] ; GFX12W64-NEXT: s_wait_kmcnt 0x0 ; GFX12W64-NEXT: s_mul_i32 s4, s6, s4 @@ -517,8 +520,8 @@ define amdgpu_kernel void @add_i32_uniform(ptr addrspace(1) %out, ptr addrspace( ; GFX12W64-NEXT: v_mov_b32_e32 v1, s4 ; GFX12W64-NEXT: buffer_atomic_add_u32 v1, off, s[8:11], null th:TH_ATOMIC_RETURN ; GFX12W64-NEXT: .LBB1_2: -; GFX12W64-NEXT: s_or_b64 exec, exec, s[2:3] -; GFX12W64-NEXT: s_load_b64 s[0:1], s[0:1], 0x24 +; GFX12W64-NEXT: s_or_b64 exec, exec, s[0:1] +; GFX12W64-NEXT: s_load_b64 s[0:1], s[2:3], 0x24 ; GFX12W64-NEXT: s_wait_loadcnt 0x0 ; GFX12W64-NEXT: v_readfirstlane_b32 s2, v1 ; GFX12W64-NEXT: s_wait_kmcnt 0x0 @@ -532,32 +535,32 @@ define amdgpu_kernel void @add_i32_uniform(ptr addrspace(1) %out, ptr addrspace( ; ; GFX12W32-LABEL: add_i32_uniform: ; GFX12W32: ; %bb.0: ; %entry -; GFX12W32-NEXT: s_load_b32 s2, s[0:1], 0x44 +; GFX12W32-NEXT: s_load_b32 s0, s[2:3], 0x44 ; GFX12W32-NEXT: s_mov_b32 s4, exec_lo -; GFX12W32-NEXT: s_mov_b32 s3, exec_lo +; GFX12W32-NEXT: s_mov_b32 s1, exec_lo ; GFX12W32-NEXT: v_mbcnt_lo_u32_b32 v0, s4, 0 ; GFX12W32-NEXT: ; implicit-def: $vgpr1 ; GFX12W32-NEXT: s_delay_alu instid0(VALU_DEP_1) ; GFX12W32-NEXT: v_cmpx_eq_u32_e32 0, v0 ; GFX12W32-NEXT: s_cbranch_execz .LBB1_2 ; GFX12W32-NEXT: ; %bb.1: -; GFX12W32-NEXT: s_load_b128 s[8:11], s[0:1], 0x34 +; GFX12W32-NEXT: s_load_b128 s[8:11], s[2:3], 0x34 ; GFX12W32-NEXT: s_bcnt1_i32_b32 s4, s4 ; GFX12W32-NEXT: s_wait_kmcnt 0x0 -; GFX12W32-NEXT: s_mul_i32 s4, s2, s4 +; GFX12W32-NEXT: s_mul_i32 s4, s0, s4 ; GFX12W32-NEXT: s_delay_alu instid0(SALU_CYCLE_1) ; GFX12W32-NEXT: v_mov_b32_e32 v1, s4 ; GFX12W32-NEXT: buffer_atomic_add_u32 v1, off, s[8:11], null th:TH_ATOMIC_RETURN ; GFX12W32-NEXT: .LBB1_2: -; GFX12W32-NEXT: s_or_b32 exec_lo, exec_lo, s3 -; GFX12W32-NEXT: s_load_b64 s[0:1], s[0:1], 0x24 +; GFX12W32-NEXT: s_or_b32 exec_lo, exec_lo, s1 +; GFX12W32-NEXT: s_load_b64 s[2:3], s[2:3], 0x24 ; GFX12W32-NEXT: s_wait_loadcnt 0x0 ; GFX12W32-NEXT: v_readfirstlane_b32 s4, v1 ; GFX12W32-NEXT: s_wait_kmcnt 0x0 ; GFX12W32-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX12W32-NEXT: v_mad_co_u64_u32 v[0:1], null, s2, v0, s[4:5] +; GFX12W32-NEXT: v_mad_co_u64_u32 v[0:1], null, s0, v0, s[4:5] ; GFX12W32-NEXT: v_mov_b32_e32 v1, 0 -; GFX12W32-NEXT: global_store_b32 v1, v0, s[0:1] +; GFX12W32-NEXT: global_store_b32 v1, v0, s[2:3] ; GFX12W32-NEXT: s_nop 0 ; GFX12W32-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) ; GFX12W32-NEXT: s_endpgm @@ -570,8 +573,8 @@ entry: define amdgpu_kernel void @add_i32_varying_vdata(ptr addrspace(1) %out, ptr addrspace(8) %inout) { ; GFX6-LABEL: add_i32_varying_vdata: ; GFX6: ; %bb.0: ; %entry -; GFX6-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0xd -; GFX6-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9 +; GFX6-NEXT: s_load_dwordx4 s[4:7], s[2:3], 0xd +; GFX6-NEXT: s_load_dwordx2 s[0:1], s[2:3], 0x9 ; GFX6-NEXT: s_waitcnt lgkmcnt(0) ; GFX6-NEXT: buffer_atomic_add v0, off, s[4:7], 0 glc ; GFX6-NEXT: s_mov_b32 s3, 0xf000 @@ -582,36 +585,36 @@ define amdgpu_kernel void @add_i32_varying_vdata(ptr addrspace(1) %out, ptr addr ; ; GFX8-LABEL: add_i32_varying_vdata: ; GFX8: ; %bb.0: ; %entry -; GFX8-NEXT: s_mov_b64 s[2:3], exec +; GFX8-NEXT: s_mov_b64 s[0:1], exec ; GFX8-NEXT: s_mov_b32 s4, 0 ; GFX8-NEXT: ; implicit-def: $vgpr1 ; GFX8-NEXT: .LBB2_1: ; %ComputeLoop ; GFX8-NEXT: ; =>This Inner Loop Header: Depth=1 -; GFX8-NEXT: s_ff1_i32_b64 s5, s[2:3] +; GFX8-NEXT: s_ff1_i32_b64 s5, s[0:1] ; GFX8-NEXT: s_mov_b32 m0, s5 ; GFX8-NEXT: v_readlane_b32 s8, v0, s5 ; GFX8-NEXT: s_lshl_b64 s[6:7], 1, s5 ; GFX8-NEXT: v_writelane_b32 v1, s4, m0 ; GFX8-NEXT: s_add_i32 s4, s4, s8 -; GFX8-NEXT: s_andn2_b64 s[2:3], s[2:3], s[6:7] -; GFX8-NEXT: s_cmp_lg_u64 s[2:3], 0 +; GFX8-NEXT: s_andn2_b64 s[0:1], s[0:1], s[6:7] +; GFX8-NEXT: s_cmp_lg_u64 s[0:1], 0 ; GFX8-NEXT: s_cbranch_scc1 .LBB2_1 ; GFX8-NEXT: ; %bb.2: ; %ComputeEnd ; GFX8-NEXT: v_mbcnt_lo_u32_b32 v0, exec_lo, 0 ; GFX8-NEXT: v_mbcnt_hi_u32_b32 v0, exec_hi, v0 ; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 ; GFX8-NEXT: ; implicit-def: $vgpr0 -; GFX8-NEXT: s_and_saveexec_b64 s[2:3], vcc -; GFX8-NEXT: s_xor_b64 s[2:3], exec, s[2:3] +; GFX8-NEXT: s_and_saveexec_b64 s[0:1], vcc +; GFX8-NEXT: s_xor_b64 s[0:1], exec, s[0:1] ; GFX8-NEXT: s_cbranch_execz .LBB2_4 ; GFX8-NEXT: ; %bb.3: -; GFX8-NEXT: s_load_dwordx4 s[8:11], s[0:1], 0x34 +; GFX8-NEXT: s_load_dwordx4 s[8:11], s[2:3], 0x34 ; GFX8-NEXT: v_mov_b32_e32 v0, s4 ; GFX8-NEXT: s_waitcnt lgkmcnt(0) ; GFX8-NEXT: buffer_atomic_add v0, off, s[8:11], 0 glc ; GFX8-NEXT: .LBB2_4: -; GFX8-NEXT: s_or_b64 exec, exec, s[2:3] -; GFX8-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 +; GFX8-NEXT: s_or_b64 exec, exec, s[0:1] +; GFX8-NEXT: s_load_dwordx2 s[0:1], s[2:3], 0x24 ; GFX8-NEXT: s_waitcnt vmcnt(0) ; GFX8-NEXT: v_readfirstlane_b32 s2, v0 ; GFX8-NEXT: v_add_u32_e32 v2, vcc, s2, v1 @@ -623,36 +626,36 @@ define amdgpu_kernel void @add_i32_varying_vdata(ptr addrspace(1) %out, ptr addr ; ; GFX9-LABEL: add_i32_varying_vdata: ; GFX9: ; %bb.0: ; %entry -; GFX9-NEXT: s_mov_b64 s[2:3], exec +; GFX9-NEXT: s_mov_b64 s[0:1], exec ; GFX9-NEXT: s_mov_b32 s4, 0 ; GFX9-NEXT: ; implicit-def: $vgpr1 ; GFX9-NEXT: .LBB2_1: ; %ComputeLoop ; GFX9-NEXT: ; =>This Inner Loop Header: Depth=1 -; GFX9-NEXT: s_ff1_i32_b64 s5, s[2:3] +; GFX9-NEXT: s_ff1_i32_b64 s5, s[0:1] ; GFX9-NEXT: s_mov_b32 m0, s5 ; GFX9-NEXT: v_readlane_b32 s8, v0, s5 ; GFX9-NEXT: s_lshl_b64 s[6:7], 1, s5 ; GFX9-NEXT: v_writelane_b32 v1, s4, m0 ; GFX9-NEXT: s_add_i32 s4, s4, s8 -; GFX9-NEXT: s_andn2_b64 s[2:3], s[2:3], s[6:7] -; GFX9-NEXT: s_cmp_lg_u64 s[2:3], 0 +; GFX9-NEXT: s_andn2_b64 s[0:1], s[0:1], s[6:7] +; GFX9-NEXT: s_cmp_lg_u64 s[0:1], 0 ; GFX9-NEXT: s_cbranch_scc1 .LBB2_1 ; GFX9-NEXT: ; %bb.2: ; %ComputeEnd ; GFX9-NEXT: v_mbcnt_lo_u32_b32 v0, exec_lo, 0 ; GFX9-NEXT: v_mbcnt_hi_u32_b32 v0, exec_hi, v0 ; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 ; GFX9-NEXT: ; implicit-def: $vgpr0 -; GFX9-NEXT: s_and_saveexec_b64 s[2:3], vcc -; GFX9-NEXT: s_xor_b64 s[2:3], exec, s[2:3] +; GFX9-NEXT: s_and_saveexec_b64 s[0:1], vcc +; GFX9-NEXT: s_xor_b64 s[0:1], exec, s[0:1] ; GFX9-NEXT: s_cbranch_execz .LBB2_4 ; GFX9-NEXT: ; %bb.3: -; GFX9-NEXT: s_load_dwordx4 s[8:11], s[0:1], 0x34 +; GFX9-NEXT: s_load_dwordx4 s[8:11], s[2:3], 0x34 ; GFX9-NEXT: v_mov_b32_e32 v0, s4 ; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: buffer_atomic_add v0, off, s[8:11], 0 glc ; GFX9-NEXT: .LBB2_4: -; GFX9-NEXT: s_or_b64 exec, exec, s[2:3] -; GFX9-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 +; GFX9-NEXT: s_or_b64 exec, exec, s[0:1] +; GFX9-NEXT: s_load_dwordx2 s[0:1], s[2:3], 0x24 ; GFX9-NEXT: s_waitcnt vmcnt(0) ; GFX9-NEXT: v_readfirstlane_b32 s2, v0 ; GFX9-NEXT: v_mov_b32_e32 v2, 0 @@ -663,37 +666,38 @@ define amdgpu_kernel void @add_i32_varying_vdata(ptr addrspace(1) %out, ptr addr ; ; GFX10W64-LABEL: add_i32_varying_vdata: ; GFX10W64: ; %bb.0: ; %entry -; GFX10W64-NEXT: s_mov_b64 s[2:3], exec +; GFX10W64-NEXT: s_mov_b64 s[0:1], exec ; GFX10W64-NEXT: s_mov_b32 s4, 0 ; GFX10W64-NEXT: ; implicit-def: $vgpr1 ; GFX10W64-NEXT: .LBB2_1: ; %ComputeLoop ; GFX10W64-NEXT: ; =>This Inner Loop Header: Depth=1 -; GFX10W64-NEXT: s_ff1_i32_b64 s5, s[2:3] +; GFX10W64-NEXT: s_ff1_i32_b64 s5, s[0:1] ; GFX10W64-NEXT: v_readlane_b32 s8, v0, s5 ; GFX10W64-NEXT: s_lshl_b64 s[6:7], 1, s5 ; GFX10W64-NEXT: v_writelane_b32 v1, s4, s5 -; GFX10W64-NEXT: s_andn2_b64 s[2:3], s[2:3], s[6:7] +; GFX10W64-NEXT: s_andn2_b64 s[0:1], s[0:1], s[6:7] ; GFX10W64-NEXT: s_add_i32 s4, s4, s8 -; GFX10W64-NEXT: s_cmp_lg_u64 s[2:3], 0 +; GFX10W64-NEXT: s_cmp_lg_u64 s[0:1], 0 ; GFX10W64-NEXT: s_cbranch_scc1 .LBB2_1 ; GFX10W64-NEXT: ; %bb.2: ; %ComputeEnd ; GFX10W64-NEXT: v_mbcnt_lo_u32_b32 v0, exec_lo, 0 ; GFX10W64-NEXT: v_mbcnt_hi_u32_b32 v0, exec_hi, v0 ; GFX10W64-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 ; GFX10W64-NEXT: ; implicit-def: $vgpr0 -; GFX10W64-NEXT: s_and_saveexec_b64 s[2:3], vcc -; GFX10W64-NEXT: s_xor_b64 s[2:3], exec, s[2:3] +; GFX10W64-NEXT: s_and_saveexec_b64 s[0:1], vcc +; GFX10W64-NEXT: s_xor_b64 s[0:1], exec, s[0:1] ; GFX10W64-NEXT: s_cbranch_execz .LBB2_4 ; GFX10W64-NEXT: ; %bb.3: -; GFX10W64-NEXT: s_load_dwordx4 s[8:11], s[0:1], 0x34 +; GFX10W64-NEXT: s_load_dwordx4 s[8:11], s[2:3], 0x34 ; GFX10W64-NEXT: v_mov_b32_e32 v0, s4 ; GFX10W64-NEXT: s_waitcnt lgkmcnt(0) ; GFX10W64-NEXT: buffer_atomic_add v0, off, s[8:11], 0 glc ; GFX10W64-NEXT: .LBB2_4: ; GFX10W64-NEXT: s_waitcnt_depctr 0xffe3 -; GFX10W64-NEXT: s_or_b64 exec, exec, s[2:3] -; GFX10W64-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 +; GFX10W64-NEXT: s_or_b64 exec, exec, s[0:1] +; GFX10W64-NEXT: s_load_dwordx2 s[0:1], s[2:3], 0x24 ; GFX10W64-NEXT: s_waitcnt vmcnt(0) +; GFX10W64-NEXT: s_mov_b32 null, 0 ; GFX10W64-NEXT: v_readfirstlane_b32 s2, v0 ; GFX10W64-NEXT: v_mov_b32_e32 v0, 0 ; GFX10W64-NEXT: v_add_nc_u32_e32 v1, s2, v1 @@ -703,36 +707,37 @@ define amdgpu_kernel void @add_i32_varying_vdata(ptr addrspace(1) %out, ptr addr ; ; GFX10W32-LABEL: add_i32_varying_vdata: ; GFX10W32: ; %bb.0: ; %entry -; GFX10W32-NEXT: s_mov_b32 s3, exec_lo -; GFX10W32-NEXT: s_mov_b32 s2, 0 +; GFX10W32-NEXT: s_mov_b32 s1, exec_lo +; GFX10W32-NEXT: s_mov_b32 s0, 0 ; GFX10W32-NEXT: ; implicit-def: $vgpr1 ; GFX10W32-NEXT: .LBB2_1: ; %ComputeLoop ; GFX10W32-NEXT: ; =>This Inner Loop Header: Depth=1 -; GFX10W32-NEXT: s_ff1_i32_b32 s4, s3 +; GFX10W32-NEXT: s_ff1_i32_b32 s4, s1 ; GFX10W32-NEXT: v_readlane_b32 s5, v0, s4 ; GFX10W32-NEXT: s_lshl_b32 s6, 1, s4 -; GFX10W32-NEXT: v_writelane_b32 v1, s2, s4 -; GFX10W32-NEXT: s_andn2_b32 s3, s3, s6 -; GFX10W32-NEXT: s_add_i32 s2, s2, s5 -; GFX10W32-NEXT: s_cmp_lg_u32 s3, 0 +; GFX10W32-NEXT: v_writelane_b32 v1, s0, s4 +; GFX10W32-NEXT: s_andn2_b32 s1, s1, s6 +; GFX10W32-NEXT: s_add_i32 s0, s0, s5 +; GFX10W32-NEXT: s_cmp_lg_u32 s1, 0 ; GFX10W32-NEXT: s_cbranch_scc1 .LBB2_1 ; GFX10W32-NEXT: ; %bb.2: ; %ComputeEnd ; GFX10W32-NEXT: v_mbcnt_lo_u32_b32 v0, exec_lo, 0 ; GFX10W32-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 ; GFX10W32-NEXT: ; implicit-def: $vgpr0 -; GFX10W32-NEXT: s_and_saveexec_b32 s3, vcc_lo -; GFX10W32-NEXT: s_xor_b32 s3, exec_lo, s3 +; GFX10W32-NEXT: s_and_saveexec_b32 s1, vcc_lo +; GFX10W32-NEXT: s_xor_b32 s1, exec_lo, s1 ; GFX10W32-NEXT: s_cbranch_execz .LBB2_4 ; GFX10W32-NEXT: ; %bb.3: -; GFX10W32-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x34 -; GFX10W32-NEXT: v_mov_b32_e32 v0, s2 +; GFX10W32-NEXT: s_load_dwordx4 s[4:7], s[2:3], 0x34 +; GFX10W32-NEXT: v_mov_b32_e32 v0, s0 ; GFX10W32-NEXT: s_waitcnt lgkmcnt(0) ; GFX10W32-NEXT: buffer_atomic_add v0, off, s[4:7], 0 glc ; GFX10W32-NEXT: .LBB2_4: ; GFX10W32-NEXT: s_waitcnt_depctr 0xffe3 -; GFX10W32-NEXT: s_or_b32 exec_lo, exec_lo, s3 -; GFX10W32-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 +; GFX10W32-NEXT: s_or_b32 exec_lo, exec_lo, s1 +; GFX10W32-NEXT: s_load_dwordx2 s[0:1], s[2:3], 0x24 ; GFX10W32-NEXT: s_waitcnt vmcnt(0) +; GFX10W32-NEXT: s_mov_b32 null, 0 ; GFX10W32-NEXT: v_readfirstlane_b32 s2, v0 ; GFX10W32-NEXT: v_mov_b32_e32 v0, 0 ; GFX10W32-NEXT: v_add_nc_u32_e32 v1, s2, v1 @@ -742,174 +747,182 @@ define amdgpu_kernel void @add_i32_varying_vdata(ptr addrspace(1) %out, ptr addr ; ; GFX11W64-LABEL: add_i32_varying_vdata: ; GFX11W64: ; %bb.0: ; %entry -; GFX11W64-NEXT: s_mov_b64 s[2:3], exec +; GFX11W64-NEXT: v_and_b32_e32 v1, 0x3ff, v0 +; GFX11W64-NEXT: s_mov_b64 s[0:1], exec ; GFX11W64-NEXT: s_mov_b32 s4, 0 -; GFX11W64-NEXT: ; implicit-def: $vgpr1 +; GFX11W64-NEXT: ; implicit-def: $vgpr0 ; GFX11W64-NEXT: .LBB2_1: ; %ComputeLoop ; GFX11W64-NEXT: ; =>This Inner Loop Header: Depth=1 -; GFX11W64-NEXT: s_ctz_i32_b64 s5, s[2:3] -; GFX11W64-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_2) -; GFX11W64-NEXT: v_readlane_b32 s8, v0, s5 +; GFX11W64-NEXT: s_ctz_i32_b64 s5, s[0:1] +; GFX11W64-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1) +; GFX11W64-NEXT: v_readlane_b32 s8, v1, s5 ; GFX11W64-NEXT: s_lshl_b64 s[6:7], 1, s5 -; GFX11W64-NEXT: v_writelane_b32 v1, s4, s5 -; GFX11W64-NEXT: s_and_not1_b64 s[2:3], s[2:3], s[6:7] +; GFX11W64-NEXT: v_writelane_b32 v0, s4, s5 +; GFX11W64-NEXT: s_and_not1_b64 s[0:1], s[0:1], s[6:7] +; GFX11W64-NEXT: s_delay_alu instid0(VALU_DEP_2) ; GFX11W64-NEXT: s_add_i32 s4, s4, s8 -; GFX11W64-NEXT: s_cmp_lg_u64 s[2:3], 0 +; GFX11W64-NEXT: s_cmp_lg_u64 s[0:1], 0 ; GFX11W64-NEXT: s_cbranch_scc1 .LBB2_1 ; GFX11W64-NEXT: ; %bb.2: ; %ComputeEnd -; GFX11W64-NEXT: v_mbcnt_lo_u32_b32 v0, exec_lo, 0 +; GFX11W64-NEXT: v_mbcnt_lo_u32_b32 v1, exec_lo, 0 ; GFX11W64-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11W64-NEXT: v_mbcnt_hi_u32_b32 v0, exec_hi, v0 -; GFX11W64-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 -; GFX11W64-NEXT: ; implicit-def: $vgpr0 -; GFX11W64-NEXT: s_and_saveexec_b64 s[2:3], vcc +; GFX11W64-NEXT: v_mbcnt_hi_u32_b32 v1, exec_hi, v1 +; GFX11W64-NEXT: v_cmp_eq_u32_e32 vcc, 0, v1 +; GFX11W64-NEXT: ; implicit-def: $vgpr1 +; GFX11W64-NEXT: s_and_saveexec_b64 s[0:1], vcc ; GFX11W64-NEXT: s_delay_alu instid0(SALU_CYCLE_1) -; GFX11W64-NEXT: s_xor_b64 s[2:3], exec, s[2:3] +; GFX11W64-NEXT: s_xor_b64 s[0:1], exec, s[0:1] ; GFX11W64-NEXT: s_cbranch_execz .LBB2_4 ; GFX11W64-NEXT: ; %bb.3: -; GFX11W64-NEXT: s_load_b128 s[8:11], s[0:1], 0x34 -; GFX11W64-NEXT: v_mov_b32_e32 v0, s4 +; GFX11W64-NEXT: s_load_b128 s[8:11], s[2:3], 0x34 +; GFX11W64-NEXT: v_mov_b32_e32 v1, s4 ; GFX11W64-NEXT: s_waitcnt lgkmcnt(0) -; GFX11W64-NEXT: buffer_atomic_add_u32 v0, off, s[8:11], 0 glc +; GFX11W64-NEXT: buffer_atomic_add_u32 v1, off, s[8:11], 0 glc ; GFX11W64-NEXT: .LBB2_4: -; GFX11W64-NEXT: s_or_b64 exec, exec, s[2:3] -; GFX11W64-NEXT: s_load_b64 s[0:1], s[0:1], 0x24 +; GFX11W64-NEXT: s_or_b64 exec, exec, s[0:1] +; GFX11W64-NEXT: s_load_b64 s[0:1], s[2:3], 0x24 ; GFX11W64-NEXT: s_waitcnt vmcnt(0) -; GFX11W64-NEXT: v_readfirstlane_b32 s2, v0 -; GFX11W64-NEXT: v_mov_b32_e32 v0, 0 +; GFX11W64-NEXT: v_readfirstlane_b32 s2, v1 +; GFX11W64-NEXT: v_mov_b32_e32 v1, 0 ; GFX11W64-NEXT: s_delay_alu instid0(VALU_DEP_2) -; GFX11W64-NEXT: v_add_nc_u32_e32 v1, s2, v1 +; GFX11W64-NEXT: v_add_nc_u32_e32 v0, s2, v0 ; GFX11W64-NEXT: s_waitcnt lgkmcnt(0) -; GFX11W64-NEXT: global_store_b32 v0, v1, s[0:1] +; GFX11W64-NEXT: global_store_b32 v1, v0, s[0:1] ; GFX11W64-NEXT: s_nop 0 ; GFX11W64-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) ; GFX11W64-NEXT: s_endpgm ; ; GFX11W32-LABEL: add_i32_varying_vdata: ; GFX11W32: ; %bb.0: ; %entry -; GFX11W32-NEXT: s_mov_b32 s3, exec_lo -; GFX11W32-NEXT: s_mov_b32 s2, 0 -; GFX11W32-NEXT: ; implicit-def: $vgpr1 +; GFX11W32-NEXT: v_and_b32_e32 v1, 0x3ff, v0 +; GFX11W32-NEXT: s_mov_b32 s1, exec_lo +; GFX11W32-NEXT: s_mov_b32 s0, 0 +; GFX11W32-NEXT: ; implicit-def: $vgpr0 ; GFX11W32-NEXT: .LBB2_1: ; %ComputeLoop ; GFX11W32-NEXT: ; =>This Inner Loop Header: Depth=1 -; GFX11W32-NEXT: s_ctz_i32_b32 s4, s3 -; GFX11W32-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_2) -; GFX11W32-NEXT: v_readlane_b32 s5, v0, s4 +; GFX11W32-NEXT: s_ctz_i32_b32 s4, s1 +; GFX11W32-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1) +; GFX11W32-NEXT: v_readlane_b32 s5, v1, s4 ; GFX11W32-NEXT: s_lshl_b32 s6, 1, s4 -; GFX11W32-NEXT: v_writelane_b32 v1, s2, s4 -; GFX11W32-NEXT: s_and_not1_b32 s3, s3, s6 -; GFX11W32-NEXT: s_add_i32 s2, s2, s5 -; GFX11W32-NEXT: s_cmp_lg_u32 s3, 0 +; GFX11W32-NEXT: v_writelane_b32 v0, s0, s4 +; GFX11W32-NEXT: s_and_not1_b32 s1, s1, s6 +; GFX11W32-NEXT: s_delay_alu instid0(VALU_DEP_2) +; GFX11W32-NEXT: s_add_i32 s0, s0, s5 +; GFX11W32-NEXT: s_cmp_lg_u32 s1, 0 ; GFX11W32-NEXT: s_cbranch_scc1 .LBB2_1 ; GFX11W32-NEXT: ; %bb.2: ; %ComputeEnd -; GFX11W32-NEXT: v_mbcnt_lo_u32_b32 v0, exec_lo, 0 +; GFX11W32-NEXT: v_mbcnt_lo_u32_b32 v1, exec_lo, 0 ; GFX11W32-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1) -; GFX11W32-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 -; GFX11W32-NEXT: ; implicit-def: $vgpr0 -; GFX11W32-NEXT: s_and_saveexec_b32 s3, vcc_lo -; GFX11W32-NEXT: s_xor_b32 s3, exec_lo, s3 +; GFX11W32-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1 +; GFX11W32-NEXT: ; implicit-def: $vgpr1 +; GFX11W32-NEXT: s_and_saveexec_b32 s1, vcc_lo +; GFX11W32-NEXT: s_xor_b32 s1, exec_lo, s1 ; GFX11W32-NEXT: s_cbranch_execz .LBB2_4 ; GFX11W32-NEXT: ; %bb.3: -; GFX11W32-NEXT: s_load_b128 s[4:7], s[0:1], 0x34 -; GFX11W32-NEXT: v_mov_b32_e32 v0, s2 +; GFX11W32-NEXT: s_load_b128 s[4:7], s[2:3], 0x34 +; GFX11W32-NEXT: v_mov_b32_e32 v1, s0 ; GFX11W32-NEXT: s_waitcnt lgkmcnt(0) -; GFX11W32-NEXT: buffer_atomic_add_u32 v0, off, s[4:7], 0 glc +; GFX11W32-NEXT: buffer_atomic_add_u32 v1, off, s[4:7], 0 glc ; GFX11W32-NEXT: .LBB2_4: -; GFX11W32-NEXT: s_or_b32 exec_lo, exec_lo, s3 -; GFX11W32-NEXT: s_load_b64 s[0:1], s[0:1], 0x24 +; GFX11W32-NEXT: s_or_b32 exec_lo, exec_lo, s1 +; GFX11W32-NEXT: s_load_b64 s[0:1], s[2:3], 0x24 ; GFX11W32-NEXT: s_waitcnt vmcnt(0) -; GFX11W32-NEXT: v_readfirstlane_b32 s2, v0 +; GFX11W32-NEXT: v_readfirstlane_b32 s2, v1 ; GFX11W32-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11W32-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_add_nc_u32 v1, s2, v1 +; GFX11W32-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_add_nc_u32 v0, s2, v0 ; GFX11W32-NEXT: s_waitcnt lgkmcnt(0) -; GFX11W32-NEXT: global_store_b32 v0, v1, s[0:1] +; GFX11W32-NEXT: global_store_b32 v1, v0, s[0:1] ; GFX11W32-NEXT: s_nop 0 ; GFX11W32-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) ; GFX11W32-NEXT: s_endpgm ; ; GFX12W64-LABEL: add_i32_varying_vdata: ; GFX12W64: ; %bb.0: ; %entry -; GFX12W64-NEXT: s_mov_b64 s[2:3], exec +; GFX12W64-NEXT: v_and_b32_e32 v1, 0x3ff, v0 +; GFX12W64-NEXT: s_mov_b64 s[0:1], exec ; GFX12W64-NEXT: s_mov_b32 s4, 0 -; GFX12W64-NEXT: ; implicit-def: $vgpr1 +; GFX12W64-NEXT: ; implicit-def: $vgpr0 ; GFX12W64-NEXT: .LBB2_1: ; %ComputeLoop ; GFX12W64-NEXT: ; =>This Inner Loop Header: Depth=1 -; GFX12W64-NEXT: s_ctz_i32_b64 s5, s[2:3] -; GFX12W64-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_2) -; GFX12W64-NEXT: v_readlane_b32 s8, v0, s5 +; GFX12W64-NEXT: s_ctz_i32_b64 s5, s[0:1] +; GFX12W64-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1) +; GFX12W64-NEXT: v_readlane_b32 s8, v1, s5 ; GFX12W64-NEXT: s_lshl_b64 s[6:7], 1, s5 -; GFX12W64-NEXT: v_writelane_b32 v1, s4, s5 -; GFX12W64-NEXT: s_and_not1_b64 s[2:3], s[2:3], s[6:7] +; GFX12W64-NEXT: v_writelane_b32 v0, s4, s5 +; GFX12W64-NEXT: s_and_not1_b64 s[0:1], s[0:1], s[6:7] +; GFX12W64-NEXT: s_delay_alu instid0(VALU_DEP_2) ; GFX12W64-NEXT: s_add_co_i32 s4, s4, s8 -; GFX12W64-NEXT: s_cmp_lg_u64 s[2:3], 0 +; GFX12W64-NEXT: s_cmp_lg_u64 s[0:1], 0 ; GFX12W64-NEXT: s_cbranch_scc1 .LBB2_1 ; GFX12W64-NEXT: ; %bb.2: ; %ComputeEnd -; GFX12W64-NEXT: v_mbcnt_lo_u32_b32 v0, exec_lo, 0 +; GFX12W64-NEXT: v_mbcnt_lo_u32_b32 v1, exec_lo, 0 ; GFX12W64-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX12W64-NEXT: v_mbcnt_hi_u32_b32 v0, exec_hi, v0 -; GFX12W64-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 -; GFX12W64-NEXT: ; implicit-def: $vgpr0 -; GFX12W64-NEXT: s_and_saveexec_b64 s[2:3], vcc +; GFX12W64-NEXT: v_mbcnt_hi_u32_b32 v1, exec_hi, v1 +; GFX12W64-NEXT: v_cmp_eq_u32_e32 vcc, 0, v1 +; GFX12W64-NEXT: ; implicit-def: $vgpr1 +; GFX12W64-NEXT: s_and_saveexec_b64 s[0:1], vcc ; GFX12W64-NEXT: s_delay_alu instid0(SALU_CYCLE_1) -; GFX12W64-NEXT: s_xor_b64 s[2:3], exec, s[2:3] +; GFX12W64-NEXT: s_xor_b64 s[0:1], exec, s[0:1] ; GFX12W64-NEXT: s_cbranch_execz .LBB2_4 ; GFX12W64-NEXT: ; %bb.3: -; GFX12W64-NEXT: s_load_b128 s[8:11], s[0:1], 0x34 -; GFX12W64-NEXT: v_mov_b32_e32 v0, s4 +; GFX12W64-NEXT: s_load_b128 s[8:11], s[2:3], 0x34 +; GFX12W64-NEXT: v_mov_b32_e32 v1, s4 ; GFX12W64-NEXT: s_wait_kmcnt 0x0 -; GFX12W64-NEXT: buffer_atomic_add_u32 v0, off, s[8:11], null th:TH_ATOMIC_RETURN +; GFX12W64-NEXT: buffer_atomic_add_u32 v1, off, s[8:11], null th:TH_ATOMIC_RETURN ; GFX12W64-NEXT: .LBB2_4: -; GFX12W64-NEXT: s_or_b64 exec, exec, s[2:3] -; GFX12W64-NEXT: s_load_b64 s[0:1], s[0:1], 0x24 +; GFX12W64-NEXT: s_or_b64 exec, exec, s[0:1] +; GFX12W64-NEXT: s_load_b64 s[0:1], s[2:3], 0x24 ; GFX12W64-NEXT: s_wait_loadcnt 0x0 -; GFX12W64-NEXT: v_readfirstlane_b32 s2, v0 -; GFX12W64-NEXT: v_mov_b32_e32 v0, 0 +; GFX12W64-NEXT: v_readfirstlane_b32 s2, v1 +; GFX12W64-NEXT: v_mov_b32_e32 v1, 0 ; GFX12W64-NEXT: s_delay_alu instid0(VALU_DEP_2) -; GFX12W64-NEXT: v_add_nc_u32_e32 v1, s2, v1 +; GFX12W64-NEXT: v_add_nc_u32_e32 v0, s2, v0 ; GFX12W64-NEXT: s_wait_kmcnt 0x0 -; GFX12W64-NEXT: global_store_b32 v0, v1, s[0:1] +; GFX12W64-NEXT: global_store_b32 v1, v0, s[0:1] ; GFX12W64-NEXT: s_nop 0 ; GFX12W64-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) ; GFX12W64-NEXT: s_endpgm ; ; GFX12W32-LABEL: add_i32_varying_vdata: ; GFX12W32: ; %bb.0: ; %entry -; GFX12W32-NEXT: s_mov_b32 s3, exec_lo -; GFX12W32-NEXT: s_mov_b32 s2, 0 -; GFX12W32-NEXT: ; implicit-def: $vgpr1 +; GFX12W32-NEXT: v_and_b32_e32 v1, 0x3ff, v0 +; GFX12W32-NEXT: s_mov_b32 s1, exec_lo +; GFX12W32-NEXT: s_mov_b32 s0, 0 +; GFX12W32-NEXT: ; implicit-def: $vgpr0 ; GFX12W32-NEXT: .LBB2_1: ; %ComputeLoop ; GFX12W32-NEXT: ; =>This Inner Loop Header: Depth=1 -; GFX12W32-NEXT: s_ctz_i32_b32 s4, s3 -; GFX12W32-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_2) -; GFX12W32-NEXT: v_readlane_b32 s5, v0, s4 +; GFX12W32-NEXT: s_ctz_i32_b32 s4, s1 +; GFX12W32-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1) +; GFX12W32-NEXT: v_readlane_b32 s5, v1, s4 ; GFX12W32-NEXT: s_lshl_b32 s6, 1, s4 -; GFX12W32-NEXT: v_writelane_b32 v1, s2, s4 -; GFX12W32-NEXT: s_and_not1_b32 s3, s3, s6 -; GFX12W32-NEXT: s_add_co_i32 s2, s2, s5 -; GFX12W32-NEXT: s_cmp_lg_u32 s3, 0 +; GFX12W32-NEXT: v_writelane_b32 v0, s0, s4 +; GFX12W32-NEXT: s_and_not1_b32 s1, s1, s6 +; GFX12W32-NEXT: s_delay_alu instid0(VALU_DEP_2) +; GFX12W32-NEXT: s_add_co_i32 s0, s0, s5 +; GFX12W32-NEXT: s_cmp_lg_u32 s1, 0 ; GFX12W32-NEXT: s_cbranch_scc1 .LBB2_1 ; GFX12W32-NEXT: ; %bb.2: ; %ComputeEnd -; GFX12W32-NEXT: v_mbcnt_lo_u32_b32 v0, exec_lo, 0 +; GFX12W32-NEXT: v_mbcnt_lo_u32_b32 v1, exec_lo, 0 ; GFX12W32-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1) -; GFX12W32-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 -; GFX12W32-NEXT: ; implicit-def: $vgpr0 -; GFX12W32-NEXT: s_and_saveexec_b32 s3, vcc_lo -; GFX12W32-NEXT: s_xor_b32 s3, exec_lo, s3 +; GFX12W32-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1 +; GFX12W32-NEXT: ; implicit-def: $vgpr1 +; GFX12W32-NEXT: s_and_saveexec_b32 s1, vcc_lo +; GFX12W32-NEXT: s_xor_b32 s1, exec_lo, s1 ; GFX12W32-NEXT: s_cbranch_execz .LBB2_4 ; GFX12W32-NEXT: ; %bb.3: -; GFX12W32-NEXT: s_load_b128 s[4:7], s[0:1], 0x34 -; GFX12W32-NEXT: v_mov_b32_e32 v0, s2 +; GFX12W32-NEXT: s_load_b128 s[4:7], s[2:3], 0x34 +; GFX12W32-NEXT: v_mov_b32_e32 v1, s0 ; GFX12W32-NEXT: s_wait_kmcnt 0x0 -; GFX12W32-NEXT: buffer_atomic_add_u32 v0, off, s[4:7], null th:TH_ATOMIC_RETURN +; GFX12W32-NEXT: buffer_atomic_add_u32 v1, off, s[4:7], null th:TH_ATOMIC_RETURN ; GFX12W32-NEXT: .LBB2_4: -; GFX12W32-NEXT: s_or_b32 exec_lo, exec_lo, s3 -; GFX12W32-NEXT: s_load_b64 s[0:1], s[0:1], 0x24 +; GFX12W32-NEXT: s_or_b32 exec_lo, exec_lo, s1 +; GFX12W32-NEXT: s_load_b64 s[0:1], s[2:3], 0x24 ; GFX12W32-NEXT: s_wait_loadcnt 0x0 -; GFX12W32-NEXT: v_readfirstlane_b32 s2, v0 +; GFX12W32-NEXT: v_readfirstlane_b32 s2, v1 ; GFX12W32-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX12W32-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_add_nc_u32 v1, s2, v1 +; GFX12W32-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_add_nc_u32 v0, s2, v0 ; GFX12W32-NEXT: s_wait_kmcnt 0x0 -; GFX12W32-NEXT: global_store_b32 v0, v1, s[0:1] +; GFX12W32-NEXT: global_store_b32 v1, v0, s[0:1] ; GFX12W32-NEXT: s_nop 0 ; GFX12W32-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) ; GFX12W32-NEXT: s_endpgm @@ -923,8 +936,8 @@ entry: define amdgpu_kernel void @add_i32_varying_offset(ptr addrspace(1) %out, ptr addrspace(8) %inout) { ; GFX6-LABEL: add_i32_varying_offset: ; GFX6: ; %bb.0: ; %entry -; GFX6-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0xd -; GFX6-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9 +; GFX6-NEXT: s_load_dwordx4 s[4:7], s[2:3], 0xd +; GFX6-NEXT: s_load_dwordx2 s[0:1], s[2:3], 0x9 ; GFX6-NEXT: v_mov_b32_e32 v1, 1 ; GFX6-NEXT: s_waitcnt lgkmcnt(0) ; GFX6-NEXT: buffer_atomic_add v1, v0, s[4:7], 0 offen glc @@ -936,9 +949,9 @@ define amdgpu_kernel void @add_i32_varying_offset(ptr addrspace(1) %out, ptr add ; ; GFX8-LABEL: add_i32_varying_offset: ; GFX8: ; %bb.0: ; %entry -; GFX8-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x34 +; GFX8-NEXT: s_load_dwordx4 s[4:7], s[2:3], 0x34 +; GFX8-NEXT: s_load_dwordx2 s[0:1], s[2:3], 0x24 ; GFX8-NEXT: v_mov_b32_e32 v2, 1 -; GFX8-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 ; GFX8-NEXT: s_waitcnt lgkmcnt(0) ; GFX8-NEXT: buffer_atomic_add v2, v0, s[4:7], 0 offen glc ; GFX8-NEXT: v_mov_b32_e32 v0, s0 @@ -949,9 +962,9 @@ define amdgpu_kernel void @add_i32_varying_offset(ptr addrspace(1) %out, ptr add ; ; GFX9-LABEL: add_i32_varying_offset: ; GFX9: ; %bb.0: ; %entry -; GFX9-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x34 +; GFX9-NEXT: s_load_dwordx4 s[4:7], s[2:3], 0x34 +; GFX9-NEXT: s_load_dwordx2 s[0:1], s[2:3], 0x24 ; GFX9-NEXT: v_mov_b32_e32 v1, 1 -; GFX9-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 ; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: buffer_atomic_add v1, v0, s[4:7], 0 offen glc ; GFX9-NEXT: v_mov_b32_e32 v0, 0 @@ -961,9 +974,10 @@ define amdgpu_kernel void @add_i32_varying_offset(ptr addrspace(1) %out, ptr add ; ; GFX10-LABEL: add_i32_varying_offset: ; GFX10: ; %bb.0: ; %entry -; GFX10-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x34 +; GFX10-NEXT: s_clause 0x1 +; GFX10-NEXT: s_load_dwordx4 s[4:7], s[2:3], 0x34 +; GFX10-NEXT: s_load_dwordx2 s[0:1], s[2:3], 0x24 ; GFX10-NEXT: v_mov_b32_e32 v1, 1 -; GFX10-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 ; GFX10-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-NEXT: buffer_atomic_add v1, v0, s[4:7], 0 offen glc ; GFX10-NEXT: v_mov_b32_e32 v0, 0 @@ -971,33 +985,67 @@ define amdgpu_kernel void @add_i32_varying_offset(ptr addrspace(1) %out, ptr add ; GFX10-NEXT: global_store_dword v0, v1, s[0:1] ; GFX10-NEXT: s_endpgm ; -; GFX11-LABEL: add_i32_varying_offset: -; GFX11: ; %bb.0: ; %entry -; GFX11-NEXT: s_load_b128 s[4:7], s[0:1], 0x34 -; GFX11-NEXT: v_mov_b32_e32 v1, 1 -; GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x24 -; GFX11-NEXT: s_waitcnt lgkmcnt(0) -; GFX11-NEXT: buffer_atomic_add_u32 v1, v0, s[4:7], 0 offen glc -; GFX11-NEXT: v_mov_b32_e32 v0, 0 -; GFX11-NEXT: s_waitcnt vmcnt(0) -; GFX11-NEXT: global_store_b32 v0, v1, s[0:1] -; GFX11-NEXT: s_nop 0 -; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) -; GFX11-NEXT: s_endpgm +; GFX11W64-LABEL: add_i32_varying_offset: +; GFX11W64: ; %bb.0: ; %entry +; GFX11W64-NEXT: s_clause 0x1 +; GFX11W64-NEXT: s_load_b128 s[4:7], s[2:3], 0x34 +; GFX11W64-NEXT: s_load_b64 s[0:1], s[2:3], 0x24 +; GFX11W64-NEXT: v_and_b32_e32 v0, 0x3ff, v0 +; GFX11W64-NEXT: v_mov_b32_e32 v1, 1 +; GFX11W64-NEXT: s_waitcnt lgkmcnt(0) +; GFX11W64-NEXT: buffer_atomic_add_u32 v1, v0, s[4:7], 0 offen glc +; GFX11W64-NEXT: v_mov_b32_e32 v0, 0 +; GFX11W64-NEXT: s_waitcnt vmcnt(0) +; GFX11W64-NEXT: global_store_b32 v0, v1, s[0:1] +; GFX11W64-NEXT: s_nop 0 +; GFX11W64-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GFX11W64-NEXT: s_endpgm +; +; GFX11W32-LABEL: add_i32_varying_offset: +; GFX11W32: ; %bb.0: ; %entry +; GFX11W32-NEXT: s_clause 0x1 +; GFX11W32-NEXT: s_load_b128 s[4:7], s[2:3], 0x34 +; GFX11W32-NEXT: s_load_b64 s[0:1], s[2:3], 0x24 +; GFX11W32-NEXT: v_dual_mov_b32 v1, 1 :: v_dual_and_b32 v0, 0x3ff, v0 +; GFX11W32-NEXT: s_waitcnt lgkmcnt(0) +; GFX11W32-NEXT: buffer_atomic_add_u32 v1, v0, s[4:7], 0 offen glc +; GFX11W32-NEXT: v_mov_b32_e32 v0, 0 +; GFX11W32-NEXT: s_waitcnt vmcnt(0) +; GFX11W32-NEXT: global_store_b32 v0, v1, s[0:1] +; GFX11W32-NEXT: s_nop 0 +; GFX11W32-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GFX11W32-NEXT: s_endpgm ; -; GFX12-LABEL: add_i32_varying_offset: -; GFX12: ; %bb.0: ; %entry -; GFX12-NEXT: s_load_b128 s[4:7], s[0:1], 0x34 -; GFX12-NEXT: v_mov_b32_e32 v1, 1 -; GFX12-NEXT: s_load_b64 s[0:1], s[0:1], 0x24 -; GFX12-NEXT: s_wait_kmcnt 0x0 -; GFX12-NEXT: buffer_atomic_add_u32 v1, v0, s[4:7], null offen th:TH_ATOMIC_RETURN -; GFX12-NEXT: v_mov_b32_e32 v0, 0 -; GFX12-NEXT: s_wait_loadcnt 0x0 -; GFX12-NEXT: global_store_b32 v0, v1, s[0:1] -; GFX12-NEXT: s_nop 0 -; GFX12-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) -; GFX12-NEXT: s_endpgm +; GFX12W64-LABEL: add_i32_varying_offset: +; GFX12W64: ; %bb.0: ; %entry +; GFX12W64-NEXT: s_clause 0x1 +; GFX12W64-NEXT: s_load_b128 s[4:7], s[2:3], 0x34 +; GFX12W64-NEXT: s_load_b64 s[0:1], s[2:3], 0x24 +; GFX12W64-NEXT: v_and_b32_e32 v0, 0x3ff, v0 +; GFX12W64-NEXT: v_mov_b32_e32 v1, 1 +; GFX12W64-NEXT: s_wait_kmcnt 0x0 +; GFX12W64-NEXT: buffer_atomic_add_u32 v1, v0, s[4:7], null offen th:TH_ATOMIC_RETURN +; GFX12W64-NEXT: v_mov_b32_e32 v0, 0 +; GFX12W64-NEXT: s_wait_loadcnt 0x0 +; GFX12W64-NEXT: global_store_b32 v0, v1, s[0:1] +; GFX12W64-NEXT: s_nop 0 +; GFX12W64-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GFX12W64-NEXT: s_endpgm +; +; GFX12W32-LABEL: add_i32_varying_offset: +; GFX12W32: ; %bb.0: ; %entry +; GFX12W32-NEXT: s_clause 0x1 +; GFX12W32-NEXT: s_load_b128 s[4:7], s[2:3], 0x34 +; GFX12W32-NEXT: s_load_b64 s[0:1], s[2:3], 0x24 +; GFX12W32-NEXT: v_dual_mov_b32 v1, 1 :: v_dual_and_b32 v0, 0x3ff, v0 +; GFX12W32-NEXT: s_wait_kmcnt 0x0 +; GFX12W32-NEXT: buffer_atomic_add_u32 v1, v0, s[4:7], null offen th:TH_ATOMIC_RETURN +; GFX12W32-NEXT: v_mov_b32_e32 v0, 0 +; GFX12W32-NEXT: s_wait_loadcnt 0x0 +; GFX12W32-NEXT: global_store_b32 v0, v1, s[0:1] +; GFX12W32-NEXT: s_nop 0 +; GFX12W32-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GFX12W32-NEXT: s_endpgm entry: %lane = call i32 @llvm.amdgcn.workitem.id.x() %old = call i32 @llvm.amdgcn.raw.ptr.buffer.atomic.add(i32 1, ptr addrspace(8) %inout, i32 %lane, i32 0, i32 0) @@ -1013,18 +1061,18 @@ define amdgpu_kernel void @sub_i32_constant(ptr addrspace(1) %out, ptr addrspace ; GFX6-NEXT: v_mbcnt_hi_u32_b32_e32 v0, s5, v0 ; GFX6-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 ; GFX6-NEXT: ; implicit-def: $vgpr1 -; GFX6-NEXT: s_and_saveexec_b64 s[2:3], vcc +; GFX6-NEXT: s_and_saveexec_b64 s[0:1], vcc ; GFX6-NEXT: s_cbranch_execz .LBB4_2 ; GFX6-NEXT: ; %bb.1: -; GFX6-NEXT: s_load_dwordx4 s[8:11], s[0:1], 0xd +; GFX6-NEXT: s_load_dwordx4 s[8:11], s[2:3], 0xd ; GFX6-NEXT: s_bcnt1_i32_b64 s4, s[4:5] ; GFX6-NEXT: s_mul_i32 s4, s4, 5 ; GFX6-NEXT: v_mov_b32_e32 v1, s4 ; GFX6-NEXT: s_waitcnt lgkmcnt(0) ; GFX6-NEXT: buffer_atomic_sub v1, off, s[8:11], 0 glc ; GFX6-NEXT: .LBB4_2: -; GFX6-NEXT: s_or_b64 exec, exec, s[2:3] -; GFX6-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9 +; GFX6-NEXT: s_or_b64 exec, exec, s[0:1] +; GFX6-NEXT: s_load_dwordx2 s[0:1], s[2:3], 0x9 ; GFX6-NEXT: s_mov_b32 s3, 0xf000 ; GFX6-NEXT: s_mov_b32 s2, -1 ; GFX6-NEXT: s_waitcnt vmcnt(0) @@ -1042,18 +1090,18 @@ define amdgpu_kernel void @sub_i32_constant(ptr addrspace(1) %out, ptr addrspace ; GFX8-NEXT: v_mbcnt_hi_u32_b32 v0, s5, v0 ; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 ; GFX8-NEXT: ; implicit-def: $vgpr1 -; GFX8-NEXT: s_and_saveexec_b64 s[2:3], vcc +; GFX8-NEXT: s_and_saveexec_b64 s[0:1], vcc ; GFX8-NEXT: s_cbranch_execz .LBB4_2 ; GFX8-NEXT: ; %bb.1: -; GFX8-NEXT: s_load_dwordx4 s[8:11], s[0:1], 0x34 +; GFX8-NEXT: s_load_dwordx4 s[8:11], s[2:3], 0x34 ; GFX8-NEXT: s_bcnt1_i32_b64 s4, s[4:5] ; GFX8-NEXT: s_mul_i32 s4, s4, 5 ; GFX8-NEXT: v_mov_b32_e32 v1, s4 ; GFX8-NEXT: s_waitcnt lgkmcnt(0) ; GFX8-NEXT: buffer_atomic_sub v1, off, s[8:11], 0 glc ; GFX8-NEXT: .LBB4_2: -; GFX8-NEXT: s_or_b64 exec, exec, s[2:3] -; GFX8-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 +; GFX8-NEXT: s_or_b64 exec, exec, s[0:1] +; GFX8-NEXT: s_load_dwordx2 s[0:1], s[2:3], 0x24 ; GFX8-NEXT: s_waitcnt vmcnt(0) ; GFX8-NEXT: v_readfirstlane_b32 s2, v1 ; GFX8-NEXT: v_mul_u32_u24_e32 v0, 5, v0 @@ -1071,18 +1119,18 @@ define amdgpu_kernel void @sub_i32_constant(ptr addrspace(1) %out, ptr addrspace ; GFX9-NEXT: v_mbcnt_hi_u32_b32 v0, s5, v0 ; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 ; GFX9-NEXT: ; implicit-def: $vgpr1 -; GFX9-NEXT: s_and_saveexec_b64 s[2:3], vcc +; GFX9-NEXT: s_and_saveexec_b64 s[0:1], vcc ; GFX9-NEXT: s_cbranch_execz .LBB4_2 ; GFX9-NEXT: ; %bb.1: -; GFX9-NEXT: s_load_dwordx4 s[8:11], s[0:1], 0x34 +; GFX9-NEXT: s_load_dwordx4 s[8:11], s[2:3], 0x34 ; GFX9-NEXT: s_bcnt1_i32_b64 s4, s[4:5] ; GFX9-NEXT: s_mul_i32 s4, s4, 5 ; GFX9-NEXT: v_mov_b32_e32 v1, s4 ; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: buffer_atomic_sub v1, off, s[8:11], 0 glc ; GFX9-NEXT: .LBB4_2: -; GFX9-NEXT: s_or_b64 exec, exec, s[2:3] -; GFX9-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 +; GFX9-NEXT: s_or_b64 exec, exec, s[0:1] +; GFX9-NEXT: s_load_dwordx2 s[0:1], s[2:3], 0x24 ; GFX9-NEXT: s_waitcnt vmcnt(0) ; GFX9-NEXT: v_readfirstlane_b32 s2, v1 ; GFX9-NEXT: v_mul_u32_u24_e32 v0, 5, v0 @@ -1099,10 +1147,10 @@ define amdgpu_kernel void @sub_i32_constant(ptr addrspace(1) %out, ptr addrspace ; GFX10W64-NEXT: v_mbcnt_lo_u32_b32 v0, s4, 0 ; GFX10W64-NEXT: v_mbcnt_hi_u32_b32 v0, s5, v0 ; GFX10W64-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 -; GFX10W64-NEXT: s_and_saveexec_b64 s[2:3], vcc +; GFX10W64-NEXT: s_and_saveexec_b64 s[0:1], vcc ; GFX10W64-NEXT: s_cbranch_execz .LBB4_2 ; GFX10W64-NEXT: ; %bb.1: -; GFX10W64-NEXT: s_load_dwordx4 s[8:11], s[0:1], 0x34 +; GFX10W64-NEXT: s_load_dwordx4 s[8:11], s[2:3], 0x34 ; GFX10W64-NEXT: s_bcnt1_i32_b64 s4, s[4:5] ; GFX10W64-NEXT: s_mul_i32 s4, s4, 5 ; GFX10W64-NEXT: v_mov_b32_e32 v1, s4 @@ -1110,9 +1158,10 @@ define amdgpu_kernel void @sub_i32_constant(ptr addrspace(1) %out, ptr addrspace ; GFX10W64-NEXT: buffer_atomic_sub v1, off, s[8:11], 0 glc ; GFX10W64-NEXT: .LBB4_2: ; GFX10W64-NEXT: s_waitcnt_depctr 0xffe3 -; GFX10W64-NEXT: s_or_b64 exec, exec, s[2:3] -; GFX10W64-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 +; GFX10W64-NEXT: s_or_b64 exec, exec, s[0:1] +; GFX10W64-NEXT: s_load_dwordx2 s[0:1], s[2:3], 0x24 ; GFX10W64-NEXT: s_waitcnt vmcnt(0) +; GFX10W64-NEXT: s_mov_b32 null, 0 ; GFX10W64-NEXT: v_readfirstlane_b32 s2, v1 ; GFX10W64-NEXT: v_mul_u32_u24_e32 v0, 5, v0 ; GFX10W64-NEXT: v_mov_b32_e32 v1, 0 @@ -1123,24 +1172,25 @@ define amdgpu_kernel void @sub_i32_constant(ptr addrspace(1) %out, ptr addrspace ; ; GFX10W32-LABEL: sub_i32_constant: ; GFX10W32: ; %bb.0: ; %entry -; GFX10W32-NEXT: s_mov_b32 s3, exec_lo +; GFX10W32-NEXT: s_mov_b32 s1, exec_lo ; GFX10W32-NEXT: ; implicit-def: $vgpr1 -; GFX10W32-NEXT: v_mbcnt_lo_u32_b32 v0, s3, 0 +; GFX10W32-NEXT: v_mbcnt_lo_u32_b32 v0, s1, 0 ; GFX10W32-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 -; GFX10W32-NEXT: s_and_saveexec_b32 s2, vcc_lo +; GFX10W32-NEXT: s_and_saveexec_b32 s0, vcc_lo ; GFX10W32-NEXT: s_cbranch_execz .LBB4_2 ; GFX10W32-NEXT: ; %bb.1: -; GFX10W32-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x34 -; GFX10W32-NEXT: s_bcnt1_i32_b32 s3, s3 -; GFX10W32-NEXT: s_mul_i32 s3, s3, 5 -; GFX10W32-NEXT: v_mov_b32_e32 v1, s3 +; GFX10W32-NEXT: s_load_dwordx4 s[4:7], s[2:3], 0x34 +; GFX10W32-NEXT: s_bcnt1_i32_b32 s1, s1 +; GFX10W32-NEXT: s_mul_i32 s1, s1, 5 +; GFX10W32-NEXT: v_mov_b32_e32 v1, s1 ; GFX10W32-NEXT: s_waitcnt lgkmcnt(0) ; GFX10W32-NEXT: buffer_atomic_sub v1, off, s[4:7], 0 glc ; GFX10W32-NEXT: .LBB4_2: ; GFX10W32-NEXT: s_waitcnt_depctr 0xffe3 -; GFX10W32-NEXT: s_or_b32 exec_lo, exec_lo, s2 -; GFX10W32-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 +; GFX10W32-NEXT: s_or_b32 exec_lo, exec_lo, s0 +; GFX10W32-NEXT: s_load_dwordx2 s[0:1], s[2:3], 0x24 ; GFX10W32-NEXT: s_waitcnt vmcnt(0) +; GFX10W32-NEXT: s_mov_b32 null, 0 ; GFX10W32-NEXT: v_readfirstlane_b32 s2, v1 ; GFX10W32-NEXT: v_mul_u32_u24_e32 v0, 5, v0 ; GFX10W32-NEXT: v_mov_b32_e32 v1, 0 @@ -1152,7 +1202,7 @@ define amdgpu_kernel void @sub_i32_constant(ptr addrspace(1) %out, ptr addrspace ; GFX11W64-LABEL: sub_i32_constant: ; GFX11W64: ; %bb.0: ; %entry ; GFX11W64-NEXT: s_mov_b64 s[4:5], exec -; GFX11W64-NEXT: s_mov_b64 s[2:3], exec +; GFX11W64-NEXT: s_mov_b64 s[0:1], exec ; GFX11W64-NEXT: v_mbcnt_lo_u32_b32 v0, s4, 0 ; GFX11W64-NEXT: ; implicit-def: $vgpr1 ; GFX11W64-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) @@ -1160,7 +1210,7 @@ define amdgpu_kernel void @sub_i32_constant(ptr addrspace(1) %out, ptr addrspace ; GFX11W64-NEXT: v_cmpx_eq_u32_e32 0, v0 ; GFX11W64-NEXT: s_cbranch_execz .LBB4_2 ; GFX11W64-NEXT: ; %bb.1: -; GFX11W64-NEXT: s_load_b128 s[8:11], s[0:1], 0x34 +; GFX11W64-NEXT: s_load_b128 s[8:11], s[2:3], 0x34 ; GFX11W64-NEXT: s_bcnt1_i32_b64 s4, s[4:5] ; GFX11W64-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) ; GFX11W64-NEXT: s_mul_i32 s4, s4, 5 @@ -1168,8 +1218,8 @@ define amdgpu_kernel void @sub_i32_constant(ptr addrspace(1) %out, ptr addrspace ; GFX11W64-NEXT: s_waitcnt lgkmcnt(0) ; GFX11W64-NEXT: buffer_atomic_sub_u32 v1, off, s[8:11], 0 glc ; GFX11W64-NEXT: .LBB4_2: -; GFX11W64-NEXT: s_or_b64 exec, exec, s[2:3] -; GFX11W64-NEXT: s_load_b64 s[0:1], s[0:1], 0x24 +; GFX11W64-NEXT: s_or_b64 exec, exec, s[0:1] +; GFX11W64-NEXT: s_load_b64 s[0:1], s[2:3], 0x24 ; GFX11W64-NEXT: s_waitcnt vmcnt(0) ; GFX11W64-NEXT: v_readfirstlane_b32 s2, v1 ; GFX11W64-NEXT: v_mul_u32_u24_e32 v0, 5, v0 @@ -1184,24 +1234,24 @@ define amdgpu_kernel void @sub_i32_constant(ptr addrspace(1) %out, ptr addrspace ; ; GFX11W32-LABEL: sub_i32_constant: ; GFX11W32: ; %bb.0: ; %entry -; GFX11W32-NEXT: s_mov_b32 s3, exec_lo -; GFX11W32-NEXT: s_mov_b32 s2, exec_lo -; GFX11W32-NEXT: v_mbcnt_lo_u32_b32 v0, s3, 0 +; GFX11W32-NEXT: s_mov_b32 s1, exec_lo +; GFX11W32-NEXT: s_mov_b32 s0, exec_lo +; GFX11W32-NEXT: v_mbcnt_lo_u32_b32 v0, s1, 0 ; GFX11W32-NEXT: ; implicit-def: $vgpr1 ; GFX11W32-NEXT: s_delay_alu instid0(VALU_DEP_1) ; GFX11W32-NEXT: v_cmpx_eq_u32_e32 0, v0 ; GFX11W32-NEXT: s_cbranch_execz .LBB4_2 ; GFX11W32-NEXT: ; %bb.1: -; GFX11W32-NEXT: s_load_b128 s[4:7], s[0:1], 0x34 -; GFX11W32-NEXT: s_bcnt1_i32_b32 s3, s3 +; GFX11W32-NEXT: s_load_b128 s[4:7], s[2:3], 0x34 +; GFX11W32-NEXT: s_bcnt1_i32_b32 s1, s1 ; GFX11W32-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) -; GFX11W32-NEXT: s_mul_i32 s3, s3, 5 -; GFX11W32-NEXT: v_mov_b32_e32 v1, s3 +; GFX11W32-NEXT: s_mul_i32 s1, s1, 5 +; GFX11W32-NEXT: v_mov_b32_e32 v1, s1 ; GFX11W32-NEXT: s_waitcnt lgkmcnt(0) ; GFX11W32-NEXT: buffer_atomic_sub_u32 v1, off, s[4:7], 0 glc ; GFX11W32-NEXT: .LBB4_2: -; GFX11W32-NEXT: s_or_b32 exec_lo, exec_lo, s2 -; GFX11W32-NEXT: s_load_b64 s[0:1], s[0:1], 0x24 +; GFX11W32-NEXT: s_or_b32 exec_lo, exec_lo, s0 +; GFX11W32-NEXT: s_load_b64 s[0:1], s[2:3], 0x24 ; GFX11W32-NEXT: s_waitcnt vmcnt(0) ; GFX11W32-NEXT: v_readfirstlane_b32 s2, v1 ; GFX11W32-NEXT: v_mul_u32_u24_e32 v0, 5, v0 @@ -1217,7 +1267,7 @@ define amdgpu_kernel void @sub_i32_constant(ptr addrspace(1) %out, ptr addrspace ; GFX12W64-LABEL: sub_i32_constant: ; GFX12W64: ; %bb.0: ; %entry ; GFX12W64-NEXT: s_mov_b64 s[4:5], exec -; GFX12W64-NEXT: s_mov_b64 s[2:3], exec +; GFX12W64-NEXT: s_mov_b64 s[0:1], exec ; GFX12W64-NEXT: v_mbcnt_lo_u32_b32 v0, s4, 0 ; GFX12W64-NEXT: ; implicit-def: $vgpr1 ; GFX12W64-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) @@ -1225,7 +1275,7 @@ define amdgpu_kernel void @sub_i32_constant(ptr addrspace(1) %out, ptr addrspace ; GFX12W64-NEXT: v_cmpx_eq_u32_e32 0, v0 ; GFX12W64-NEXT: s_cbranch_execz .LBB4_2 ; GFX12W64-NEXT: ; %bb.1: -; GFX12W64-NEXT: s_load_b128 s[8:11], s[0:1], 0x34 +; GFX12W64-NEXT: s_load_b128 s[8:11], s[2:3], 0x34 ; GFX12W64-NEXT: s_bcnt1_i32_b64 s4, s[4:5] ; GFX12W64-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) ; GFX12W64-NEXT: s_mul_i32 s4, s4, 5 @@ -1233,8 +1283,8 @@ define amdgpu_kernel void @sub_i32_constant(ptr addrspace(1) %out, ptr addrspace ; GFX12W64-NEXT: s_wait_kmcnt 0x0 ; GFX12W64-NEXT: buffer_atomic_sub_u32 v1, off, s[8:11], null th:TH_ATOMIC_RETURN ; GFX12W64-NEXT: .LBB4_2: -; GFX12W64-NEXT: s_or_b64 exec, exec, s[2:3] -; GFX12W64-NEXT: s_load_b64 s[0:1], s[0:1], 0x24 +; GFX12W64-NEXT: s_or_b64 exec, exec, s[0:1] +; GFX12W64-NEXT: s_load_b64 s[0:1], s[2:3], 0x24 ; GFX12W64-NEXT: s_wait_loadcnt 0x0 ; GFX12W64-NEXT: v_readfirstlane_b32 s2, v1 ; GFX12W64-NEXT: v_mul_u32_u24_e32 v0, 5, v0 @@ -1249,24 +1299,24 @@ define amdgpu_kernel void @sub_i32_constant(ptr addrspace(1) %out, ptr addrspace ; ; GFX12W32-LABEL: sub_i32_constant: ; GFX12W32: ; %bb.0: ; %entry -; GFX12W32-NEXT: s_mov_b32 s3, exec_lo -; GFX12W32-NEXT: s_mov_b32 s2, exec_lo -; GFX12W32-NEXT: v_mbcnt_lo_u32_b32 v0, s3, 0 +; GFX12W32-NEXT: s_mov_b32 s1, exec_lo +; GFX12W32-NEXT: s_mov_b32 s0, exec_lo +; GFX12W32-NEXT: v_mbcnt_lo_u32_b32 v0, s1, 0 ; GFX12W32-NEXT: ; implicit-def: $vgpr1 ; GFX12W32-NEXT: s_delay_alu instid0(VALU_DEP_1) ; GFX12W32-NEXT: v_cmpx_eq_u32_e32 0, v0 ; GFX12W32-NEXT: s_cbranch_execz .LBB4_2 ; GFX12W32-NEXT: ; %bb.1: -; GFX12W32-NEXT: s_load_b128 s[4:7], s[0:1], 0x34 -; GFX12W32-NEXT: s_bcnt1_i32_b32 s3, s3 +; GFX12W32-NEXT: s_load_b128 s[4:7], s[2:3], 0x34 +; GFX12W32-NEXT: s_bcnt1_i32_b32 s1, s1 ; GFX12W32-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) -; GFX12W32-NEXT: s_mul_i32 s3, s3, 5 -; GFX12W32-NEXT: v_mov_b32_e32 v1, s3 +; GFX12W32-NEXT: s_mul_i32 s1, s1, 5 +; GFX12W32-NEXT: v_mov_b32_e32 v1, s1 ; GFX12W32-NEXT: s_wait_kmcnt 0x0 ; GFX12W32-NEXT: buffer_atomic_sub_u32 v1, off, s[4:7], null th:TH_ATOMIC_RETURN ; GFX12W32-NEXT: .LBB4_2: -; GFX12W32-NEXT: s_or_b32 exec_lo, exec_lo, s2 -; GFX12W32-NEXT: s_load_b64 s[0:1], s[0:1], 0x24 +; GFX12W32-NEXT: s_or_b32 exec_lo, exec_lo, s0 +; GFX12W32-NEXT: s_load_b64 s[0:1], s[2:3], 0x24 ; GFX12W32-NEXT: s_wait_loadcnt 0x0 ; GFX12W32-NEXT: v_readfirstlane_b32 s2, v1 ; GFX12W32-NEXT: v_mul_u32_u24_e32 v0, 5, v0 @@ -1288,23 +1338,23 @@ define amdgpu_kernel void @sub_i32_uniform(ptr addrspace(1) %out, ptr addrspace( ; GFX6-LABEL: sub_i32_uniform: ; GFX6: ; %bb.0: ; %entry ; GFX6-NEXT: s_mov_b64 s[4:5], exec -; GFX6-NEXT: s_load_dword s6, s[0:1], 0x11 +; GFX6-NEXT: s_load_dword s6, s[2:3], 0x11 ; GFX6-NEXT: v_mbcnt_lo_u32_b32_e64 v0, s4, 0 ; GFX6-NEXT: v_mbcnt_hi_u32_b32_e32 v0, s5, v0 ; GFX6-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 ; GFX6-NEXT: ; implicit-def: $vgpr1 -; GFX6-NEXT: s_and_saveexec_b64 s[2:3], vcc +; GFX6-NEXT: s_and_saveexec_b64 s[0:1], vcc ; GFX6-NEXT: s_cbranch_execz .LBB5_2 ; GFX6-NEXT: ; %bb.1: -; GFX6-NEXT: s_load_dwordx4 s[8:11], s[0:1], 0xd +; GFX6-NEXT: s_load_dwordx4 s[8:11], s[2:3], 0xd ; GFX6-NEXT: s_bcnt1_i32_b64 s4, s[4:5] ; GFX6-NEXT: s_waitcnt lgkmcnt(0) ; GFX6-NEXT: s_mul_i32 s4, s6, s4 ; GFX6-NEXT: v_mov_b32_e32 v1, s4 ; GFX6-NEXT: buffer_atomic_sub v1, off, s[8:11], 0 glc ; GFX6-NEXT: .LBB5_2: -; GFX6-NEXT: s_or_b64 exec, exec, s[2:3] -; GFX6-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9 +; GFX6-NEXT: s_or_b64 exec, exec, s[0:1] +; GFX6-NEXT: s_load_dwordx2 s[0:1], s[2:3], 0x9 ; GFX6-NEXT: s_mov_b32 s3, 0xf000 ; GFX6-NEXT: s_mov_b32 s2, -1 ; GFX6-NEXT: s_waitcnt vmcnt(0) @@ -1317,24 +1367,24 @@ define amdgpu_kernel void @sub_i32_uniform(ptr addrspace(1) %out, ptr addrspace( ; ; GFX8-LABEL: sub_i32_uniform: ; GFX8: ; %bb.0: ; %entry -; GFX8-NEXT: s_load_dword s6, s[0:1], 0x44 +; GFX8-NEXT: s_load_dword s6, s[2:3], 0x44 ; GFX8-NEXT: s_mov_b64 s[4:5], exec ; GFX8-NEXT: v_mbcnt_lo_u32_b32 v0, s4, 0 ; GFX8-NEXT: v_mbcnt_hi_u32_b32 v0, s5, v0 ; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 ; GFX8-NEXT: ; implicit-def: $vgpr1 -; GFX8-NEXT: s_and_saveexec_b64 s[2:3], vcc +; GFX8-NEXT: s_and_saveexec_b64 s[0:1], vcc ; GFX8-NEXT: s_cbranch_execz .LBB5_2 ; GFX8-NEXT: ; %bb.1: -; GFX8-NEXT: s_load_dwordx4 s[8:11], s[0:1], 0x34 +; GFX8-NEXT: s_load_dwordx4 s[8:11], s[2:3], 0x34 ; GFX8-NEXT: s_bcnt1_i32_b64 s4, s[4:5] ; GFX8-NEXT: s_waitcnt lgkmcnt(0) ; GFX8-NEXT: s_mul_i32 s4, s6, s4 ; GFX8-NEXT: v_mov_b32_e32 v1, s4 ; GFX8-NEXT: buffer_atomic_sub v1, off, s[8:11], 0 glc ; GFX8-NEXT: .LBB5_2: -; GFX8-NEXT: s_or_b64 exec, exec, s[2:3] -; GFX8-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 +; GFX8-NEXT: s_or_b64 exec, exec, s[0:1] +; GFX8-NEXT: s_load_dwordx2 s[0:1], s[2:3], 0x24 ; GFX8-NEXT: s_waitcnt lgkmcnt(0) ; GFX8-NEXT: v_mul_lo_u32 v0, s6, v0 ; GFX8-NEXT: s_waitcnt vmcnt(0) @@ -1347,24 +1397,24 @@ define amdgpu_kernel void @sub_i32_uniform(ptr addrspace(1) %out, ptr addrspace( ; ; GFX9-LABEL: sub_i32_uniform: ; GFX9: ; %bb.0: ; %entry -; GFX9-NEXT: s_load_dword s6, s[0:1], 0x44 +; GFX9-NEXT: s_load_dword s6, s[2:3], 0x44 ; GFX9-NEXT: s_mov_b64 s[4:5], exec ; GFX9-NEXT: v_mbcnt_lo_u32_b32 v0, s4, 0 ; GFX9-NEXT: v_mbcnt_hi_u32_b32 v0, s5, v0 ; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 ; GFX9-NEXT: ; implicit-def: $vgpr1 -; GFX9-NEXT: s_and_saveexec_b64 s[2:3], vcc +; GFX9-NEXT: s_and_saveexec_b64 s[0:1], vcc ; GFX9-NEXT: s_cbranch_execz .LBB5_2 ; GFX9-NEXT: ; %bb.1: -; GFX9-NEXT: s_load_dwordx4 s[8:11], s[0:1], 0x34 +; GFX9-NEXT: s_load_dwordx4 s[8:11], s[2:3], 0x34 ; GFX9-NEXT: s_bcnt1_i32_b64 s4, s[4:5] ; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_mul_i32 s4, s6, s4 ; GFX9-NEXT: v_mov_b32_e32 v1, s4 ; GFX9-NEXT: buffer_atomic_sub v1, off, s[8:11], 0 glc ; GFX9-NEXT: .LBB5_2: -; GFX9-NEXT: s_or_b64 exec, exec, s[2:3] -; GFX9-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 +; GFX9-NEXT: s_or_b64 exec, exec, s[0:1] +; GFX9-NEXT: s_load_dwordx2 s[0:1], s[2:3], 0x24 ; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: v_mul_lo_u32 v0, s6, v0 ; GFX9-NEXT: s_waitcnt vmcnt(0) @@ -1376,16 +1426,16 @@ define amdgpu_kernel void @sub_i32_uniform(ptr addrspace(1) %out, ptr addrspace( ; ; GFX10W64-LABEL: sub_i32_uniform: ; GFX10W64: ; %bb.0: ; %entry -; GFX10W64-NEXT: s_load_dword s6, s[0:1], 0x44 +; GFX10W64-NEXT: s_load_dword s6, s[2:3], 0x44 ; GFX10W64-NEXT: s_mov_b64 s[4:5], exec ; GFX10W64-NEXT: ; implicit-def: $vgpr1 ; GFX10W64-NEXT: v_mbcnt_lo_u32_b32 v0, s4, 0 ; GFX10W64-NEXT: v_mbcnt_hi_u32_b32 v0, s5, v0 ; GFX10W64-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 -; GFX10W64-NEXT: s_and_saveexec_b64 s[2:3], vcc +; GFX10W64-NEXT: s_and_saveexec_b64 s[0:1], vcc ; GFX10W64-NEXT: s_cbranch_execz .LBB5_2 ; GFX10W64-NEXT: ; %bb.1: -; GFX10W64-NEXT: s_load_dwordx4 s[8:11], s[0:1], 0x34 +; GFX10W64-NEXT: s_load_dwordx4 s[8:11], s[2:3], 0x34 ; GFX10W64-NEXT: s_bcnt1_i32_b64 s4, s[4:5] ; GFX10W64-NEXT: s_waitcnt lgkmcnt(0) ; GFX10W64-NEXT: s_mul_i32 s4, s6, s4 @@ -1393,8 +1443,8 @@ define amdgpu_kernel void @sub_i32_uniform(ptr addrspace(1) %out, ptr addrspace( ; GFX10W64-NEXT: buffer_atomic_sub v1, off, s[8:11], 0 glc ; GFX10W64-NEXT: .LBB5_2: ; GFX10W64-NEXT: s_waitcnt_depctr 0xffe3 -; GFX10W64-NEXT: s_or_b64 exec, exec, s[2:3] -; GFX10W64-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 +; GFX10W64-NEXT: s_or_b64 exec, exec, s[0:1] +; GFX10W64-NEXT: s_load_dwordx2 s[0:1], s[2:3], 0x24 ; GFX10W64-NEXT: s_waitcnt lgkmcnt(0) ; GFX10W64-NEXT: v_mul_lo_u32 v0, s6, v0 ; GFX10W64-NEXT: s_waitcnt vmcnt(0) @@ -1406,38 +1456,38 @@ define amdgpu_kernel void @sub_i32_uniform(ptr addrspace(1) %out, ptr addrspace( ; ; GFX10W32-LABEL: sub_i32_uniform: ; GFX10W32: ; %bb.0: ; %entry -; GFX10W32-NEXT: s_load_dword s2, s[0:1], 0x44 +; GFX10W32-NEXT: s_load_dword s0, s[2:3], 0x44 ; GFX10W32-NEXT: s_mov_b32 s4, exec_lo ; GFX10W32-NEXT: ; implicit-def: $vgpr1 ; GFX10W32-NEXT: v_mbcnt_lo_u32_b32 v0, s4, 0 ; GFX10W32-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 -; GFX10W32-NEXT: s_and_saveexec_b32 s3, vcc_lo +; GFX10W32-NEXT: s_and_saveexec_b32 s1, vcc_lo ; GFX10W32-NEXT: s_cbranch_execz .LBB5_2 ; GFX10W32-NEXT: ; %bb.1: -; GFX10W32-NEXT: s_load_dwordx4 s[8:11], s[0:1], 0x34 +; GFX10W32-NEXT: s_load_dwordx4 s[8:11], s[2:3], 0x34 ; GFX10W32-NEXT: s_bcnt1_i32_b32 s4, s4 ; GFX10W32-NEXT: s_waitcnt lgkmcnt(0) -; GFX10W32-NEXT: s_mul_i32 s4, s2, s4 +; GFX10W32-NEXT: s_mul_i32 s4, s0, s4 ; GFX10W32-NEXT: v_mov_b32_e32 v1, s4 ; GFX10W32-NEXT: buffer_atomic_sub v1, off, s[8:11], 0 glc ; GFX10W32-NEXT: .LBB5_2: ; GFX10W32-NEXT: s_waitcnt_depctr 0xffe3 -; GFX10W32-NEXT: s_or_b32 exec_lo, exec_lo, s3 -; GFX10W32-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 +; GFX10W32-NEXT: s_or_b32 exec_lo, exec_lo, s1 +; GFX10W32-NEXT: s_load_dwordx2 s[2:3], s[2:3], 0x24 ; GFX10W32-NEXT: s_waitcnt lgkmcnt(0) -; GFX10W32-NEXT: v_mul_lo_u32 v0, s2, v0 +; GFX10W32-NEXT: v_mul_lo_u32 v0, s0, v0 ; GFX10W32-NEXT: s_waitcnt vmcnt(0) -; GFX10W32-NEXT: v_readfirstlane_b32 s2, v1 +; GFX10W32-NEXT: v_readfirstlane_b32 s0, v1 ; GFX10W32-NEXT: v_mov_b32_e32 v1, 0 -; GFX10W32-NEXT: v_sub_nc_u32_e32 v0, s2, v0 -; GFX10W32-NEXT: global_store_dword v1, v0, s[0:1] +; GFX10W32-NEXT: v_sub_nc_u32_e32 v0, s0, v0 +; GFX10W32-NEXT: global_store_dword v1, v0, s[2:3] ; GFX10W32-NEXT: s_endpgm ; ; GFX11W64-LABEL: sub_i32_uniform: ; GFX11W64: ; %bb.0: ; %entry -; GFX11W64-NEXT: s_load_b32 s6, s[0:1], 0x44 +; GFX11W64-NEXT: s_load_b32 s6, s[2:3], 0x44 ; GFX11W64-NEXT: s_mov_b64 s[4:5], exec -; GFX11W64-NEXT: s_mov_b64 s[2:3], exec +; GFX11W64-NEXT: s_mov_b64 s[0:1], exec ; GFX11W64-NEXT: v_mbcnt_lo_u32_b32 v0, s4, 0 ; GFX11W64-NEXT: ; implicit-def: $vgpr1 ; GFX11W64-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) @@ -1445,7 +1495,7 @@ define amdgpu_kernel void @sub_i32_uniform(ptr addrspace(1) %out, ptr addrspace( ; GFX11W64-NEXT: v_cmpx_eq_u32_e32 0, v0 ; GFX11W64-NEXT: s_cbranch_execz .LBB5_2 ; GFX11W64-NEXT: ; %bb.1: -; GFX11W64-NEXT: s_load_b128 s[8:11], s[0:1], 0x34 +; GFX11W64-NEXT: s_load_b128 s[8:11], s[2:3], 0x34 ; GFX11W64-NEXT: s_bcnt1_i32_b64 s4, s[4:5] ; GFX11W64-NEXT: s_waitcnt lgkmcnt(0) ; GFX11W64-NEXT: s_mul_i32 s4, s6, s4 @@ -1453,8 +1503,8 @@ define amdgpu_kernel void @sub_i32_uniform(ptr addrspace(1) %out, ptr addrspace( ; GFX11W64-NEXT: v_mov_b32_e32 v1, s4 ; GFX11W64-NEXT: buffer_atomic_sub_u32 v1, off, s[8:11], 0 glc ; GFX11W64-NEXT: .LBB5_2: -; GFX11W64-NEXT: s_or_b64 exec, exec, s[2:3] -; GFX11W64-NEXT: s_load_b64 s[0:1], s[0:1], 0x24 +; GFX11W64-NEXT: s_or_b64 exec, exec, s[0:1] +; GFX11W64-NEXT: s_load_b64 s[0:1], s[2:3], 0x24 ; GFX11W64-NEXT: s_waitcnt lgkmcnt(0) ; GFX11W64-NEXT: v_mul_lo_u32 v0, s6, v0 ; GFX11W64-NEXT: s_waitcnt vmcnt(0) @@ -1469,42 +1519,42 @@ define amdgpu_kernel void @sub_i32_uniform(ptr addrspace(1) %out, ptr addrspace( ; ; GFX11W32-LABEL: sub_i32_uniform: ; GFX11W32: ; %bb.0: ; %entry -; GFX11W32-NEXT: s_load_b32 s2, s[0:1], 0x44 +; GFX11W32-NEXT: s_load_b32 s0, s[2:3], 0x44 ; GFX11W32-NEXT: s_mov_b32 s4, exec_lo -; GFX11W32-NEXT: s_mov_b32 s3, exec_lo +; GFX11W32-NEXT: s_mov_b32 s1, exec_lo ; GFX11W32-NEXT: v_mbcnt_lo_u32_b32 v0, s4, 0 ; GFX11W32-NEXT: ; implicit-def: $vgpr1 ; GFX11W32-NEXT: s_delay_alu instid0(VALU_DEP_1) ; GFX11W32-NEXT: v_cmpx_eq_u32_e32 0, v0 ; GFX11W32-NEXT: s_cbranch_execz .LBB5_2 ; GFX11W32-NEXT: ; %bb.1: -; GFX11W32-NEXT: s_load_b128 s[8:11], s[0:1], 0x34 +; GFX11W32-NEXT: s_load_b128 s[8:11], s[2:3], 0x34 ; GFX11W32-NEXT: s_bcnt1_i32_b32 s4, s4 ; GFX11W32-NEXT: s_waitcnt lgkmcnt(0) -; GFX11W32-NEXT: s_mul_i32 s4, s2, s4 +; GFX11W32-NEXT: s_mul_i32 s4, s0, s4 ; GFX11W32-NEXT: s_delay_alu instid0(SALU_CYCLE_1) ; GFX11W32-NEXT: v_mov_b32_e32 v1, s4 ; GFX11W32-NEXT: buffer_atomic_sub_u32 v1, off, s[8:11], 0 glc ; GFX11W32-NEXT: .LBB5_2: -; GFX11W32-NEXT: s_or_b32 exec_lo, exec_lo, s3 -; GFX11W32-NEXT: s_load_b64 s[0:1], s[0:1], 0x24 +; GFX11W32-NEXT: s_or_b32 exec_lo, exec_lo, s1 +; GFX11W32-NEXT: s_load_b64 s[2:3], s[2:3], 0x24 ; GFX11W32-NEXT: s_waitcnt lgkmcnt(0) -; GFX11W32-NEXT: v_mul_lo_u32 v0, s2, v0 +; GFX11W32-NEXT: v_mul_lo_u32 v0, s0, v0 ; GFX11W32-NEXT: s_waitcnt vmcnt(0) -; GFX11W32-NEXT: v_readfirstlane_b32 s2, v1 +; GFX11W32-NEXT: v_readfirstlane_b32 s0, v1 ; GFX11W32-NEXT: v_mov_b32_e32 v1, 0 ; GFX11W32-NEXT: s_delay_alu instid0(VALU_DEP_2) -; GFX11W32-NEXT: v_sub_nc_u32_e32 v0, s2, v0 -; GFX11W32-NEXT: global_store_b32 v1, v0, s[0:1] +; GFX11W32-NEXT: v_sub_nc_u32_e32 v0, s0, v0 +; GFX11W32-NEXT: global_store_b32 v1, v0, s[2:3] ; GFX11W32-NEXT: s_nop 0 ; GFX11W32-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) ; GFX11W32-NEXT: s_endpgm ; ; GFX12W64-LABEL: sub_i32_uniform: ; GFX12W64: ; %bb.0: ; %entry -; GFX12W64-NEXT: s_load_b32 s6, s[0:1], 0x44 +; GFX12W64-NEXT: s_load_b32 s6, s[2:3], 0x44 ; GFX12W64-NEXT: s_mov_b64 s[4:5], exec -; GFX12W64-NEXT: s_mov_b64 s[2:3], exec +; GFX12W64-NEXT: s_mov_b64 s[0:1], exec ; GFX12W64-NEXT: v_mbcnt_lo_u32_b32 v0, s4, 0 ; GFX12W64-NEXT: ; implicit-def: $vgpr1 ; GFX12W64-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) @@ -1512,7 +1562,7 @@ define amdgpu_kernel void @sub_i32_uniform(ptr addrspace(1) %out, ptr addrspace( ; GFX12W64-NEXT: v_cmpx_eq_u32_e32 0, v0 ; GFX12W64-NEXT: s_cbranch_execz .LBB5_2 ; GFX12W64-NEXT: ; %bb.1: -; GFX12W64-NEXT: s_load_b128 s[8:11], s[0:1], 0x34 +; GFX12W64-NEXT: s_load_b128 s[8:11], s[2:3], 0x34 ; GFX12W64-NEXT: s_bcnt1_i32_b64 s4, s[4:5] ; GFX12W64-NEXT: s_wait_kmcnt 0x0 ; GFX12W64-NEXT: s_mul_i32 s4, s6, s4 @@ -1520,8 +1570,8 @@ define amdgpu_kernel void @sub_i32_uniform(ptr addrspace(1) %out, ptr addrspace( ; GFX12W64-NEXT: v_mov_b32_e32 v1, s4 ; GFX12W64-NEXT: buffer_atomic_sub_u32 v1, off, s[8:11], null th:TH_ATOMIC_RETURN ; GFX12W64-NEXT: .LBB5_2: -; GFX12W64-NEXT: s_or_b64 exec, exec, s[2:3] -; GFX12W64-NEXT: s_load_b64 s[0:1], s[0:1], 0x24 +; GFX12W64-NEXT: s_or_b64 exec, exec, s[0:1] +; GFX12W64-NEXT: s_load_b64 s[0:1], s[2:3], 0x24 ; GFX12W64-NEXT: s_wait_kmcnt 0x0 ; GFX12W64-NEXT: v_mul_lo_u32 v0, s6, v0 ; GFX12W64-NEXT: s_wait_loadcnt 0x0 @@ -1536,33 +1586,33 @@ define amdgpu_kernel void @sub_i32_uniform(ptr addrspace(1) %out, ptr addrspace( ; ; GFX12W32-LABEL: sub_i32_uniform: ; GFX12W32: ; %bb.0: ; %entry -; GFX12W32-NEXT: s_load_b32 s2, s[0:1], 0x44 +; GFX12W32-NEXT: s_load_b32 s0, s[2:3], 0x44 ; GFX12W32-NEXT: s_mov_b32 s4, exec_lo -; GFX12W32-NEXT: s_mov_b32 s3, exec_lo +; GFX12W32-NEXT: s_mov_b32 s1, exec_lo ; GFX12W32-NEXT: v_mbcnt_lo_u32_b32 v0, s4, 0 ; GFX12W32-NEXT: ; implicit-def: $vgpr1 ; GFX12W32-NEXT: s_delay_alu instid0(VALU_DEP_1) ; GFX12W32-NEXT: v_cmpx_eq_u32_e32 0, v0 ; GFX12W32-NEXT: s_cbranch_execz .LBB5_2 ; GFX12W32-NEXT: ; %bb.1: -; GFX12W32-NEXT: s_load_b128 s[8:11], s[0:1], 0x34 +; GFX12W32-NEXT: s_load_b128 s[8:11], s[2:3], 0x34 ; GFX12W32-NEXT: s_bcnt1_i32_b32 s4, s4 ; GFX12W32-NEXT: s_wait_kmcnt 0x0 -; GFX12W32-NEXT: s_mul_i32 s4, s2, s4 +; GFX12W32-NEXT: s_mul_i32 s4, s0, s4 ; GFX12W32-NEXT: s_delay_alu instid0(SALU_CYCLE_1) ; GFX12W32-NEXT: v_mov_b32_e32 v1, s4 ; GFX12W32-NEXT: buffer_atomic_sub_u32 v1, off, s[8:11], null th:TH_ATOMIC_RETURN ; GFX12W32-NEXT: .LBB5_2: -; GFX12W32-NEXT: s_or_b32 exec_lo, exec_lo, s3 -; GFX12W32-NEXT: s_load_b64 s[0:1], s[0:1], 0x24 +; GFX12W32-NEXT: s_or_b32 exec_lo, exec_lo, s1 +; GFX12W32-NEXT: s_load_b64 s[2:3], s[2:3], 0x24 ; GFX12W32-NEXT: s_wait_kmcnt 0x0 -; GFX12W32-NEXT: v_mul_lo_u32 v0, s2, v0 +; GFX12W32-NEXT: v_mul_lo_u32 v0, s0, v0 ; GFX12W32-NEXT: s_wait_loadcnt 0x0 -; GFX12W32-NEXT: v_readfirstlane_b32 s2, v1 +; GFX12W32-NEXT: v_readfirstlane_b32 s0, v1 ; GFX12W32-NEXT: v_mov_b32_e32 v1, 0 ; GFX12W32-NEXT: s_delay_alu instid0(VALU_DEP_2) -; GFX12W32-NEXT: v_sub_nc_u32_e32 v0, s2, v0 -; GFX12W32-NEXT: global_store_b32 v1, v0, s[0:1] +; GFX12W32-NEXT: v_sub_nc_u32_e32 v0, s0, v0 +; GFX12W32-NEXT: global_store_b32 v1, v0, s[2:3] ; GFX12W32-NEXT: s_nop 0 ; GFX12W32-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) ; GFX12W32-NEXT: s_endpgm @@ -1575,8 +1625,8 @@ entry: define amdgpu_kernel void @sub_i32_varying_vdata(ptr addrspace(1) %out, ptr addrspace(8) %inout) { ; GFX6-LABEL: sub_i32_varying_vdata: ; GFX6: ; %bb.0: ; %entry -; GFX6-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0xd -; GFX6-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9 +; GFX6-NEXT: s_load_dwordx4 s[4:7], s[2:3], 0xd +; GFX6-NEXT: s_load_dwordx2 s[0:1], s[2:3], 0x9 ; GFX6-NEXT: s_waitcnt lgkmcnt(0) ; GFX6-NEXT: buffer_atomic_sub v0, off, s[4:7], 0 glc ; GFX6-NEXT: s_mov_b32 s3, 0xf000 @@ -1587,36 +1637,36 @@ define amdgpu_kernel void @sub_i32_varying_vdata(ptr addrspace(1) %out, ptr addr ; ; GFX8-LABEL: sub_i32_varying_vdata: ; GFX8: ; %bb.0: ; %entry -; GFX8-NEXT: s_mov_b64 s[2:3], exec +; GFX8-NEXT: s_mov_b64 s[0:1], exec ; GFX8-NEXT: s_mov_b32 s4, 0 ; GFX8-NEXT: ; implicit-def: $vgpr1 ; GFX8-NEXT: .LBB6_1: ; %ComputeLoop ; GFX8-NEXT: ; =>This Inner Loop Header: Depth=1 -; GFX8-NEXT: s_ff1_i32_b64 s5, s[2:3] +; GFX8-NEXT: s_ff1_i32_b64 s5, s[0:1] ; GFX8-NEXT: s_mov_b32 m0, s5 ; GFX8-NEXT: v_readlane_b32 s8, v0, s5 ; GFX8-NEXT: s_lshl_b64 s[6:7], 1, s5 ; GFX8-NEXT: v_writelane_b32 v1, s4, m0 ; GFX8-NEXT: s_add_i32 s4, s4, s8 -; GFX8-NEXT: s_andn2_b64 s[2:3], s[2:3], s[6:7] -; GFX8-NEXT: s_cmp_lg_u64 s[2:3], 0 +; GFX8-NEXT: s_andn2_b64 s[0:1], s[0:1], s[6:7] +; GFX8-NEXT: s_cmp_lg_u64 s[0:1], 0 ; GFX8-NEXT: s_cbranch_scc1 .LBB6_1 ; GFX8-NEXT: ; %bb.2: ; %ComputeEnd ; GFX8-NEXT: v_mbcnt_lo_u32_b32 v0, exec_lo, 0 ; GFX8-NEXT: v_mbcnt_hi_u32_b32 v0, exec_hi, v0 ; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 ; GFX8-NEXT: ; implicit-def: $vgpr0 -; GFX8-NEXT: s_and_saveexec_b64 s[2:3], vcc -; GFX8-NEXT: s_xor_b64 s[2:3], exec, s[2:3] +; GFX8-NEXT: s_and_saveexec_b64 s[0:1], vcc +; GFX8-NEXT: s_xor_b64 s[0:1], exec, s[0:1] ; GFX8-NEXT: s_cbranch_execz .LBB6_4 ; GFX8-NEXT: ; %bb.3: -; GFX8-NEXT: s_load_dwordx4 s[8:11], s[0:1], 0x34 +; GFX8-NEXT: s_load_dwordx4 s[8:11], s[2:3], 0x34 ; GFX8-NEXT: v_mov_b32_e32 v0, s4 ; GFX8-NEXT: s_waitcnt lgkmcnt(0) ; GFX8-NEXT: buffer_atomic_sub v0, off, s[8:11], 0 glc ; GFX8-NEXT: .LBB6_4: -; GFX8-NEXT: s_or_b64 exec, exec, s[2:3] -; GFX8-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 +; GFX8-NEXT: s_or_b64 exec, exec, s[0:1] +; GFX8-NEXT: s_load_dwordx2 s[0:1], s[2:3], 0x24 ; GFX8-NEXT: s_waitcnt vmcnt(0) ; GFX8-NEXT: v_readfirstlane_b32 s2, v0 ; GFX8-NEXT: v_sub_u32_e32 v2, vcc, s2, v1 @@ -1628,36 +1678,36 @@ define amdgpu_kernel void @sub_i32_varying_vdata(ptr addrspace(1) %out, ptr addr ; ; GFX9-LABEL: sub_i32_varying_vdata: ; GFX9: ; %bb.0: ; %entry -; GFX9-NEXT: s_mov_b64 s[2:3], exec +; GFX9-NEXT: s_mov_b64 s[0:1], exec ; GFX9-NEXT: s_mov_b32 s4, 0 ; GFX9-NEXT: ; implicit-def: $vgpr1 ; GFX9-NEXT: .LBB6_1: ; %ComputeLoop ; GFX9-NEXT: ; =>This Inner Loop Header: Depth=1 -; GFX9-NEXT: s_ff1_i32_b64 s5, s[2:3] +; GFX9-NEXT: s_ff1_i32_b64 s5, s[0:1] ; GFX9-NEXT: s_mov_b32 m0, s5 ; GFX9-NEXT: v_readlane_b32 s8, v0, s5 ; GFX9-NEXT: s_lshl_b64 s[6:7], 1, s5 ; GFX9-NEXT: v_writelane_b32 v1, s4, m0 ; GFX9-NEXT: s_add_i32 s4, s4, s8 -; GFX9-NEXT: s_andn2_b64 s[2:3], s[2:3], s[6:7] -; GFX9-NEXT: s_cmp_lg_u64 s[2:3], 0 +; GFX9-NEXT: s_andn2_b64 s[0:1], s[0:1], s[6:7] +; GFX9-NEXT: s_cmp_lg_u64 s[0:1], 0 ; GFX9-NEXT: s_cbranch_scc1 .LBB6_1 ; GFX9-NEXT: ; %bb.2: ; %ComputeEnd ; GFX9-NEXT: v_mbcnt_lo_u32_b32 v0, exec_lo, 0 ; GFX9-NEXT: v_mbcnt_hi_u32_b32 v0, exec_hi, v0 ; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 ; GFX9-NEXT: ; implicit-def: $vgpr0 -; GFX9-NEXT: s_and_saveexec_b64 s[2:3], vcc -; GFX9-NEXT: s_xor_b64 s[2:3], exec, s[2:3] +; GFX9-NEXT: s_and_saveexec_b64 s[0:1], vcc +; GFX9-NEXT: s_xor_b64 s[0:1], exec, s[0:1] ; GFX9-NEXT: s_cbranch_execz .LBB6_4 ; GFX9-NEXT: ; %bb.3: -; GFX9-NEXT: s_load_dwordx4 s[8:11], s[0:1], 0x34 +; GFX9-NEXT: s_load_dwordx4 s[8:11], s[2:3], 0x34 ; GFX9-NEXT: v_mov_b32_e32 v0, s4 ; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: buffer_atomic_sub v0, off, s[8:11], 0 glc ; GFX9-NEXT: .LBB6_4: -; GFX9-NEXT: s_or_b64 exec, exec, s[2:3] -; GFX9-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 +; GFX9-NEXT: s_or_b64 exec, exec, s[0:1] +; GFX9-NEXT: s_load_dwordx2 s[0:1], s[2:3], 0x24 ; GFX9-NEXT: s_waitcnt vmcnt(0) ; GFX9-NEXT: v_readfirstlane_b32 s2, v0 ; GFX9-NEXT: v_mov_b32_e32 v2, 0 @@ -1668,37 +1718,38 @@ define amdgpu_kernel void @sub_i32_varying_vdata(ptr addrspace(1) %out, ptr addr ; ; GFX10W64-LABEL: sub_i32_varying_vdata: ; GFX10W64: ; %bb.0: ; %entry -; GFX10W64-NEXT: s_mov_b64 s[2:3], exec +; GFX10W64-NEXT: s_mov_b64 s[0:1], exec ; GFX10W64-NEXT: s_mov_b32 s4, 0 ; GFX10W64-NEXT: ; implicit-def: $vgpr1 ; GFX10W64-NEXT: .LBB6_1: ; %ComputeLoop ; GFX10W64-NEXT: ; =>This Inner Loop Header: Depth=1 -; GFX10W64-NEXT: s_ff1_i32_b64 s5, s[2:3] +; GFX10W64-NEXT: s_ff1_i32_b64 s5, s[0:1] ; GFX10W64-NEXT: v_readlane_b32 s8, v0, s5 ; GFX10W64-NEXT: s_lshl_b64 s[6:7], 1, s5 ; GFX10W64-NEXT: v_writelane_b32 v1, s4, s5 -; GFX10W64-NEXT: s_andn2_b64 s[2:3], s[2:3], s[6:7] +; GFX10W64-NEXT: s_andn2_b64 s[0:1], s[0:1], s[6:7] ; GFX10W64-NEXT: s_add_i32 s4, s4, s8 -; GFX10W64-NEXT: s_cmp_lg_u64 s[2:3], 0 +; GFX10W64-NEXT: s_cmp_lg_u64 s[0:1], 0 ; GFX10W64-NEXT: s_cbranch_scc1 .LBB6_1 ; GFX10W64-NEXT: ; %bb.2: ; %ComputeEnd ; GFX10W64-NEXT: v_mbcnt_lo_u32_b32 v0, exec_lo, 0 ; GFX10W64-NEXT: v_mbcnt_hi_u32_b32 v0, exec_hi, v0 ; GFX10W64-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 ; GFX10W64-NEXT: ; implicit-def: $vgpr0 -; GFX10W64-NEXT: s_and_saveexec_b64 s[2:3], vcc -; GFX10W64-NEXT: s_xor_b64 s[2:3], exec, s[2:3] +; GFX10W64-NEXT: s_and_saveexec_b64 s[0:1], vcc +; GFX10W64-NEXT: s_xor_b64 s[0:1], exec, s[0:1] ; GFX10W64-NEXT: s_cbranch_execz .LBB6_4 ; GFX10W64-NEXT: ; %bb.3: -; GFX10W64-NEXT: s_load_dwordx4 s[8:11], s[0:1], 0x34 +; GFX10W64-NEXT: s_load_dwordx4 s[8:11], s[2:3], 0x34 ; GFX10W64-NEXT: v_mov_b32_e32 v0, s4 ; GFX10W64-NEXT: s_waitcnt lgkmcnt(0) ; GFX10W64-NEXT: buffer_atomic_sub v0, off, s[8:11], 0 glc ; GFX10W64-NEXT: .LBB6_4: ; GFX10W64-NEXT: s_waitcnt_depctr 0xffe3 -; GFX10W64-NEXT: s_or_b64 exec, exec, s[2:3] -; GFX10W64-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 +; GFX10W64-NEXT: s_or_b64 exec, exec, s[0:1] +; GFX10W64-NEXT: s_load_dwordx2 s[0:1], s[2:3], 0x24 ; GFX10W64-NEXT: s_waitcnt vmcnt(0) +; GFX10W64-NEXT: s_mov_b32 null, 0 ; GFX10W64-NEXT: v_readfirstlane_b32 s2, v0 ; GFX10W64-NEXT: v_mov_b32_e32 v0, 0 ; GFX10W64-NEXT: v_sub_nc_u32_e32 v1, s2, v1 @@ -1708,36 +1759,37 @@ define amdgpu_kernel void @sub_i32_varying_vdata(ptr addrspace(1) %out, ptr addr ; ; GFX10W32-LABEL: sub_i32_varying_vdata: ; GFX10W32: ; %bb.0: ; %entry -; GFX10W32-NEXT: s_mov_b32 s3, exec_lo -; GFX10W32-NEXT: s_mov_b32 s2, 0 +; GFX10W32-NEXT: s_mov_b32 s1, exec_lo +; GFX10W32-NEXT: s_mov_b32 s0, 0 ; GFX10W32-NEXT: ; implicit-def: $vgpr1 ; GFX10W32-NEXT: .LBB6_1: ; %ComputeLoop ; GFX10W32-NEXT: ; =>This Inner Loop Header: Depth=1 -; GFX10W32-NEXT: s_ff1_i32_b32 s4, s3 +; GFX10W32-NEXT: s_ff1_i32_b32 s4, s1 ; GFX10W32-NEXT: v_readlane_b32 s5, v0, s4 ; GFX10W32-NEXT: s_lshl_b32 s6, 1, s4 -; GFX10W32-NEXT: v_writelane_b32 v1, s2, s4 -; GFX10W32-NEXT: s_andn2_b32 s3, s3, s6 -; GFX10W32-NEXT: s_add_i32 s2, s2, s5 -; GFX10W32-NEXT: s_cmp_lg_u32 s3, 0 +; GFX10W32-NEXT: v_writelane_b32 v1, s0, s4 +; GFX10W32-NEXT: s_andn2_b32 s1, s1, s6 +; GFX10W32-NEXT: s_add_i32 s0, s0, s5 +; GFX10W32-NEXT: s_cmp_lg_u32 s1, 0 ; GFX10W32-NEXT: s_cbranch_scc1 .LBB6_1 ; GFX10W32-NEXT: ; %bb.2: ; %ComputeEnd ; GFX10W32-NEXT: v_mbcnt_lo_u32_b32 v0, exec_lo, 0 ; GFX10W32-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 ; GFX10W32-NEXT: ; implicit-def: $vgpr0 -; GFX10W32-NEXT: s_and_saveexec_b32 s3, vcc_lo -; GFX10W32-NEXT: s_xor_b32 s3, exec_lo, s3 +; GFX10W32-NEXT: s_and_saveexec_b32 s1, vcc_lo +; GFX10W32-NEXT: s_xor_b32 s1, exec_lo, s1 ; GFX10W32-NEXT: s_cbranch_execz .LBB6_4 ; GFX10W32-NEXT: ; %bb.3: -; GFX10W32-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x34 -; GFX10W32-NEXT: v_mov_b32_e32 v0, s2 +; GFX10W32-NEXT: s_load_dwordx4 s[4:7], s[2:3], 0x34 +; GFX10W32-NEXT: v_mov_b32_e32 v0, s0 ; GFX10W32-NEXT: s_waitcnt lgkmcnt(0) ; GFX10W32-NEXT: buffer_atomic_sub v0, off, s[4:7], 0 glc ; GFX10W32-NEXT: .LBB6_4: ; GFX10W32-NEXT: s_waitcnt_depctr 0xffe3 -; GFX10W32-NEXT: s_or_b32 exec_lo, exec_lo, s3 -; GFX10W32-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 +; GFX10W32-NEXT: s_or_b32 exec_lo, exec_lo, s1 +; GFX10W32-NEXT: s_load_dwordx2 s[0:1], s[2:3], 0x24 ; GFX10W32-NEXT: s_waitcnt vmcnt(0) +; GFX10W32-NEXT: s_mov_b32 null, 0 ; GFX10W32-NEXT: v_readfirstlane_b32 s2, v0 ; GFX10W32-NEXT: v_mov_b32_e32 v0, 0 ; GFX10W32-NEXT: v_sub_nc_u32_e32 v1, s2, v1 @@ -1747,176 +1799,184 @@ define amdgpu_kernel void @sub_i32_varying_vdata(ptr addrspace(1) %out, ptr addr ; ; GFX11W64-LABEL: sub_i32_varying_vdata: ; GFX11W64: ; %bb.0: ; %entry -; GFX11W64-NEXT: s_mov_b64 s[2:3], exec +; GFX11W64-NEXT: v_and_b32_e32 v1, 0x3ff, v0 +; GFX11W64-NEXT: s_mov_b64 s[0:1], exec ; GFX11W64-NEXT: s_mov_b32 s4, 0 -; GFX11W64-NEXT: ; implicit-def: $vgpr1 +; GFX11W64-NEXT: ; implicit-def: $vgpr0 ; GFX11W64-NEXT: .LBB6_1: ; %ComputeLoop ; GFX11W64-NEXT: ; =>This Inner Loop Header: Depth=1 -; GFX11W64-NEXT: s_ctz_i32_b64 s5, s[2:3] -; GFX11W64-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_2) -; GFX11W64-NEXT: v_readlane_b32 s8, v0, s5 +; GFX11W64-NEXT: s_ctz_i32_b64 s5, s[0:1] +; GFX11W64-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1) +; GFX11W64-NEXT: v_readlane_b32 s8, v1, s5 ; GFX11W64-NEXT: s_lshl_b64 s[6:7], 1, s5 -; GFX11W64-NEXT: v_writelane_b32 v1, s4, s5 -; GFX11W64-NEXT: s_and_not1_b64 s[2:3], s[2:3], s[6:7] +; GFX11W64-NEXT: v_writelane_b32 v0, s4, s5 +; GFX11W64-NEXT: s_and_not1_b64 s[0:1], s[0:1], s[6:7] +; GFX11W64-NEXT: s_delay_alu instid0(VALU_DEP_2) ; GFX11W64-NEXT: s_add_i32 s4, s4, s8 -; GFX11W64-NEXT: s_cmp_lg_u64 s[2:3], 0 +; GFX11W64-NEXT: s_cmp_lg_u64 s[0:1], 0 ; GFX11W64-NEXT: s_cbranch_scc1 .LBB6_1 ; GFX11W64-NEXT: ; %bb.2: ; %ComputeEnd -; GFX11W64-NEXT: v_mbcnt_lo_u32_b32 v0, exec_lo, 0 +; GFX11W64-NEXT: v_mbcnt_lo_u32_b32 v1, exec_lo, 0 ; GFX11W64-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11W64-NEXT: v_mbcnt_hi_u32_b32 v0, exec_hi, v0 -; GFX11W64-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 -; GFX11W64-NEXT: ; implicit-def: $vgpr0 -; GFX11W64-NEXT: s_and_saveexec_b64 s[2:3], vcc +; GFX11W64-NEXT: v_mbcnt_hi_u32_b32 v1, exec_hi, v1 +; GFX11W64-NEXT: v_cmp_eq_u32_e32 vcc, 0, v1 +; GFX11W64-NEXT: ; implicit-def: $vgpr1 +; GFX11W64-NEXT: s_and_saveexec_b64 s[0:1], vcc ; GFX11W64-NEXT: s_delay_alu instid0(SALU_CYCLE_1) -; GFX11W64-NEXT: s_xor_b64 s[2:3], exec, s[2:3] +; GFX11W64-NEXT: s_xor_b64 s[0:1], exec, s[0:1] ; GFX11W64-NEXT: s_cbranch_execz .LBB6_4 ; GFX11W64-NEXT: ; %bb.3: -; GFX11W64-NEXT: s_load_b128 s[8:11], s[0:1], 0x34 -; GFX11W64-NEXT: v_mov_b32_e32 v0, s4 +; GFX11W64-NEXT: s_load_b128 s[8:11], s[2:3], 0x34 +; GFX11W64-NEXT: v_mov_b32_e32 v1, s4 ; GFX11W64-NEXT: s_waitcnt lgkmcnt(0) -; GFX11W64-NEXT: buffer_atomic_sub_u32 v0, off, s[8:11], 0 glc +; GFX11W64-NEXT: buffer_atomic_sub_u32 v1, off, s[8:11], 0 glc ; GFX11W64-NEXT: .LBB6_4: -; GFX11W64-NEXT: s_or_b64 exec, exec, s[2:3] -; GFX11W64-NEXT: s_load_b64 s[0:1], s[0:1], 0x24 +; GFX11W64-NEXT: s_or_b64 exec, exec, s[0:1] +; GFX11W64-NEXT: s_load_b64 s[0:1], s[2:3], 0x24 ; GFX11W64-NEXT: s_waitcnt vmcnt(0) -; GFX11W64-NEXT: v_readfirstlane_b32 s2, v0 -; GFX11W64-NEXT: v_mov_b32_e32 v0, 0 +; GFX11W64-NEXT: v_readfirstlane_b32 s2, v1 +; GFX11W64-NEXT: v_mov_b32_e32 v1, 0 ; GFX11W64-NEXT: s_delay_alu instid0(VALU_DEP_2) -; GFX11W64-NEXT: v_sub_nc_u32_e32 v1, s2, v1 +; GFX11W64-NEXT: v_sub_nc_u32_e32 v0, s2, v0 ; GFX11W64-NEXT: s_waitcnt lgkmcnt(0) -; GFX11W64-NEXT: global_store_b32 v0, v1, s[0:1] +; GFX11W64-NEXT: global_store_b32 v1, v0, s[0:1] ; GFX11W64-NEXT: s_nop 0 ; GFX11W64-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) ; GFX11W64-NEXT: s_endpgm ; ; GFX11W32-LABEL: sub_i32_varying_vdata: ; GFX11W32: ; %bb.0: ; %entry -; GFX11W32-NEXT: s_mov_b32 s3, exec_lo -; GFX11W32-NEXT: s_mov_b32 s2, 0 -; GFX11W32-NEXT: ; implicit-def: $vgpr1 +; GFX11W32-NEXT: v_and_b32_e32 v1, 0x3ff, v0 +; GFX11W32-NEXT: s_mov_b32 s1, exec_lo +; GFX11W32-NEXT: s_mov_b32 s0, 0 +; GFX11W32-NEXT: ; implicit-def: $vgpr0 ; GFX11W32-NEXT: .LBB6_1: ; %ComputeLoop ; GFX11W32-NEXT: ; =>This Inner Loop Header: Depth=1 -; GFX11W32-NEXT: s_ctz_i32_b32 s4, s3 -; GFX11W32-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_2) -; GFX11W32-NEXT: v_readlane_b32 s5, v0, s4 +; GFX11W32-NEXT: s_ctz_i32_b32 s4, s1 +; GFX11W32-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1) +; GFX11W32-NEXT: v_readlane_b32 s5, v1, s4 ; GFX11W32-NEXT: s_lshl_b32 s6, 1, s4 -; GFX11W32-NEXT: v_writelane_b32 v1, s2, s4 -; GFX11W32-NEXT: s_and_not1_b32 s3, s3, s6 -; GFX11W32-NEXT: s_add_i32 s2, s2, s5 -; GFX11W32-NEXT: s_cmp_lg_u32 s3, 0 +; GFX11W32-NEXT: v_writelane_b32 v0, s0, s4 +; GFX11W32-NEXT: s_and_not1_b32 s1, s1, s6 +; GFX11W32-NEXT: s_delay_alu instid0(VALU_DEP_2) +; GFX11W32-NEXT: s_add_i32 s0, s0, s5 +; GFX11W32-NEXT: s_cmp_lg_u32 s1, 0 ; GFX11W32-NEXT: s_cbranch_scc1 .LBB6_1 ; GFX11W32-NEXT: ; %bb.2: ; %ComputeEnd -; GFX11W32-NEXT: v_mbcnt_lo_u32_b32 v0, exec_lo, 0 +; GFX11W32-NEXT: v_mbcnt_lo_u32_b32 v1, exec_lo, 0 ; GFX11W32-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1) -; GFX11W32-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 -; GFX11W32-NEXT: ; implicit-def: $vgpr0 -; GFX11W32-NEXT: s_and_saveexec_b32 s3, vcc_lo -; GFX11W32-NEXT: s_xor_b32 s3, exec_lo, s3 +; GFX11W32-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1 +; GFX11W32-NEXT: ; implicit-def: $vgpr1 +; GFX11W32-NEXT: s_and_saveexec_b32 s1, vcc_lo +; GFX11W32-NEXT: s_xor_b32 s1, exec_lo, s1 ; GFX11W32-NEXT: s_cbranch_execz .LBB6_4 ; GFX11W32-NEXT: ; %bb.3: -; GFX11W32-NEXT: s_load_b128 s[4:7], s[0:1], 0x34 -; GFX11W32-NEXT: v_mov_b32_e32 v0, s2 +; GFX11W32-NEXT: s_load_b128 s[4:7], s[2:3], 0x34 +; GFX11W32-NEXT: v_mov_b32_e32 v1, s0 ; GFX11W32-NEXT: s_waitcnt lgkmcnt(0) -; GFX11W32-NEXT: buffer_atomic_sub_u32 v0, off, s[4:7], 0 glc +; GFX11W32-NEXT: buffer_atomic_sub_u32 v1, off, s[4:7], 0 glc ; GFX11W32-NEXT: .LBB6_4: -; GFX11W32-NEXT: s_or_b32 exec_lo, exec_lo, s3 -; GFX11W32-NEXT: s_load_b64 s[0:1], s[0:1], 0x24 +; GFX11W32-NEXT: s_or_b32 exec_lo, exec_lo, s1 +; GFX11W32-NEXT: s_load_b64 s[0:1], s[2:3], 0x24 ; GFX11W32-NEXT: s_waitcnt vmcnt(0) -; GFX11W32-NEXT: v_readfirstlane_b32 s2, v0 -; GFX11W32-NEXT: v_mov_b32_e32 v0, 0 +; GFX11W32-NEXT: v_readfirstlane_b32 s2, v1 +; GFX11W32-NEXT: v_mov_b32_e32 v1, 0 ; GFX11W32-NEXT: s_delay_alu instid0(VALU_DEP_2) -; GFX11W32-NEXT: v_sub_nc_u32_e32 v1, s2, v1 +; GFX11W32-NEXT: v_sub_nc_u32_e32 v0, s2, v0 ; GFX11W32-NEXT: s_waitcnt lgkmcnt(0) -; GFX11W32-NEXT: global_store_b32 v0, v1, s[0:1] +; GFX11W32-NEXT: global_store_b32 v1, v0, s[0:1] ; GFX11W32-NEXT: s_nop 0 ; GFX11W32-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) ; GFX11W32-NEXT: s_endpgm ; ; GFX12W64-LABEL: sub_i32_varying_vdata: ; GFX12W64: ; %bb.0: ; %entry -; GFX12W64-NEXT: s_mov_b64 s[2:3], exec +; GFX12W64-NEXT: v_and_b32_e32 v1, 0x3ff, v0 +; GFX12W64-NEXT: s_mov_b64 s[0:1], exec ; GFX12W64-NEXT: s_mov_b32 s4, 0 -; GFX12W64-NEXT: ; implicit-def: $vgpr1 +; GFX12W64-NEXT: ; implicit-def: $vgpr0 ; GFX12W64-NEXT: .LBB6_1: ; %ComputeLoop ; GFX12W64-NEXT: ; =>This Inner Loop Header: Depth=1 -; GFX12W64-NEXT: s_ctz_i32_b64 s5, s[2:3] -; GFX12W64-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_2) -; GFX12W64-NEXT: v_readlane_b32 s8, v0, s5 +; GFX12W64-NEXT: s_ctz_i32_b64 s5, s[0:1] +; GFX12W64-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1) +; GFX12W64-NEXT: v_readlane_b32 s8, v1, s5 ; GFX12W64-NEXT: s_lshl_b64 s[6:7], 1, s5 -; GFX12W64-NEXT: v_writelane_b32 v1, s4, s5 -; GFX12W64-NEXT: s_and_not1_b64 s[2:3], s[2:3], s[6:7] +; GFX12W64-NEXT: v_writelane_b32 v0, s4, s5 +; GFX12W64-NEXT: s_and_not1_b64 s[0:1], s[0:1], s[6:7] +; GFX12W64-NEXT: s_delay_alu instid0(VALU_DEP_2) ; GFX12W64-NEXT: s_add_co_i32 s4, s4, s8 -; GFX12W64-NEXT: s_cmp_lg_u64 s[2:3], 0 +; GFX12W64-NEXT: s_cmp_lg_u64 s[0:1], 0 ; GFX12W64-NEXT: s_cbranch_scc1 .LBB6_1 ; GFX12W64-NEXT: ; %bb.2: ; %ComputeEnd -; GFX12W64-NEXT: v_mbcnt_lo_u32_b32 v0, exec_lo, 0 +; GFX12W64-NEXT: v_mbcnt_lo_u32_b32 v1, exec_lo, 0 ; GFX12W64-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX12W64-NEXT: v_mbcnt_hi_u32_b32 v0, exec_hi, v0 -; GFX12W64-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 -; GFX12W64-NEXT: ; implicit-def: $vgpr0 -; GFX12W64-NEXT: s_and_saveexec_b64 s[2:3], vcc +; GFX12W64-NEXT: v_mbcnt_hi_u32_b32 v1, exec_hi, v1 +; GFX12W64-NEXT: v_cmp_eq_u32_e32 vcc, 0, v1 +; GFX12W64-NEXT: ; implicit-def: $vgpr1 +; GFX12W64-NEXT: s_and_saveexec_b64 s[0:1], vcc ; GFX12W64-NEXT: s_delay_alu instid0(SALU_CYCLE_1) -; GFX12W64-NEXT: s_xor_b64 s[2:3], exec, s[2:3] +; GFX12W64-NEXT: s_xor_b64 s[0:1], exec, s[0:1] ; GFX12W64-NEXT: s_cbranch_execz .LBB6_4 ; GFX12W64-NEXT: ; %bb.3: -; GFX12W64-NEXT: s_load_b128 s[8:11], s[0:1], 0x34 -; GFX12W64-NEXT: v_mov_b32_e32 v0, s4 +; GFX12W64-NEXT: s_load_b128 s[8:11], s[2:3], 0x34 +; GFX12W64-NEXT: v_mov_b32_e32 v1, s4 ; GFX12W64-NEXT: s_wait_kmcnt 0x0 -; GFX12W64-NEXT: buffer_atomic_sub_u32 v0, off, s[8:11], null th:TH_ATOMIC_RETURN +; GFX12W64-NEXT: buffer_atomic_sub_u32 v1, off, s[8:11], null th:TH_ATOMIC_RETURN ; GFX12W64-NEXT: .LBB6_4: -; GFX12W64-NEXT: s_or_b64 exec, exec, s[2:3] -; GFX12W64-NEXT: s_load_b64 s[0:1], s[0:1], 0x24 +; GFX12W64-NEXT: s_or_b64 exec, exec, s[0:1] +; GFX12W64-NEXT: s_load_b64 s[0:1], s[2:3], 0x24 ; GFX12W64-NEXT: s_wait_loadcnt 0x0 -; GFX12W64-NEXT: v_readfirstlane_b32 s2, v0 -; GFX12W64-NEXT: v_mov_b32_e32 v0, 0 +; GFX12W64-NEXT: v_readfirstlane_b32 s2, v1 +; GFX12W64-NEXT: v_mov_b32_e32 v1, 0 ; GFX12W64-NEXT: s_delay_alu instid0(VALU_DEP_2) -; GFX12W64-NEXT: v_sub_nc_u32_e32 v1, s2, v1 +; GFX12W64-NEXT: v_sub_nc_u32_e32 v0, s2, v0 ; GFX12W64-NEXT: s_wait_kmcnt 0x0 -; GFX12W64-NEXT: global_store_b32 v0, v1, s[0:1] +; GFX12W64-NEXT: global_store_b32 v1, v0, s[0:1] ; GFX12W64-NEXT: s_nop 0 ; GFX12W64-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) ; GFX12W64-NEXT: s_endpgm ; ; GFX12W32-LABEL: sub_i32_varying_vdata: ; GFX12W32: ; %bb.0: ; %entry -; GFX12W32-NEXT: s_mov_b32 s3, exec_lo -; GFX12W32-NEXT: s_mov_b32 s2, 0 -; GFX12W32-NEXT: ; implicit-def: $vgpr1 +; GFX12W32-NEXT: v_and_b32_e32 v1, 0x3ff, v0 +; GFX12W32-NEXT: s_mov_b32 s1, exec_lo +; GFX12W32-NEXT: s_mov_b32 s0, 0 +; GFX12W32-NEXT: ; implicit-def: $vgpr0 ; GFX12W32-NEXT: .LBB6_1: ; %ComputeLoop ; GFX12W32-NEXT: ; =>This Inner Loop Header: Depth=1 -; GFX12W32-NEXT: s_ctz_i32_b32 s4, s3 -; GFX12W32-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_2) -; GFX12W32-NEXT: v_readlane_b32 s5, v0, s4 +; GFX12W32-NEXT: s_ctz_i32_b32 s4, s1 +; GFX12W32-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1) +; GFX12W32-NEXT: v_readlane_b32 s5, v1, s4 ; GFX12W32-NEXT: s_lshl_b32 s6, 1, s4 -; GFX12W32-NEXT: v_writelane_b32 v1, s2, s4 -; GFX12W32-NEXT: s_and_not1_b32 s3, s3, s6 -; GFX12W32-NEXT: s_add_co_i32 s2, s2, s5 -; GFX12W32-NEXT: s_cmp_lg_u32 s3, 0 +; GFX12W32-NEXT: v_writelane_b32 v0, s0, s4 +; GFX12W32-NEXT: s_and_not1_b32 s1, s1, s6 +; GFX12W32-NEXT: s_delay_alu instid0(VALU_DEP_2) +; GFX12W32-NEXT: s_add_co_i32 s0, s0, s5 +; GFX12W32-NEXT: s_cmp_lg_u32 s1, 0 ; GFX12W32-NEXT: s_cbranch_scc1 .LBB6_1 ; GFX12W32-NEXT: ; %bb.2: ; %ComputeEnd -; GFX12W32-NEXT: v_mbcnt_lo_u32_b32 v0, exec_lo, 0 +; GFX12W32-NEXT: v_mbcnt_lo_u32_b32 v1, exec_lo, 0 ; GFX12W32-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1) -; GFX12W32-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 -; GFX12W32-NEXT: ; implicit-def: $vgpr0 -; GFX12W32-NEXT: s_and_saveexec_b32 s3, vcc_lo -; GFX12W32-NEXT: s_xor_b32 s3, exec_lo, s3 +; GFX12W32-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1 +; GFX12W32-NEXT: ; implicit-def: $vgpr1 +; GFX12W32-NEXT: s_and_saveexec_b32 s1, vcc_lo +; GFX12W32-NEXT: s_xor_b32 s1, exec_lo, s1 ; GFX12W32-NEXT: s_cbranch_execz .LBB6_4 ; GFX12W32-NEXT: ; %bb.3: -; GFX12W32-NEXT: s_load_b128 s[4:7], s[0:1], 0x34 -; GFX12W32-NEXT: v_mov_b32_e32 v0, s2 +; GFX12W32-NEXT: s_load_b128 s[4:7], s[2:3], 0x34 +; GFX12W32-NEXT: v_mov_b32_e32 v1, s0 ; GFX12W32-NEXT: s_wait_kmcnt 0x0 -; GFX12W32-NEXT: buffer_atomic_sub_u32 v0, off, s[4:7], null th:TH_ATOMIC_RETURN +; GFX12W32-NEXT: buffer_atomic_sub_u32 v1, off, s[4:7], null th:TH_ATOMIC_RETURN ; GFX12W32-NEXT: .LBB6_4: -; GFX12W32-NEXT: s_or_b32 exec_lo, exec_lo, s3 -; GFX12W32-NEXT: s_load_b64 s[0:1], s[0:1], 0x24 +; GFX12W32-NEXT: s_or_b32 exec_lo, exec_lo, s1 +; GFX12W32-NEXT: s_load_b64 s[0:1], s[2:3], 0x24 ; GFX12W32-NEXT: s_wait_loadcnt 0x0 -; GFX12W32-NEXT: v_readfirstlane_b32 s2, v0 -; GFX12W32-NEXT: v_mov_b32_e32 v0, 0 +; GFX12W32-NEXT: v_readfirstlane_b32 s2, v1 +; GFX12W32-NEXT: v_mov_b32_e32 v1, 0 ; GFX12W32-NEXT: s_delay_alu instid0(VALU_DEP_2) -; GFX12W32-NEXT: v_sub_nc_u32_e32 v1, s2, v1 +; GFX12W32-NEXT: v_sub_nc_u32_e32 v0, s2, v0 ; GFX12W32-NEXT: s_wait_kmcnt 0x0 -; GFX12W32-NEXT: global_store_b32 v0, v1, s[0:1] +; GFX12W32-NEXT: global_store_b32 v1, v0, s[0:1] ; GFX12W32-NEXT: s_nop 0 ; GFX12W32-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) ; GFX12W32-NEXT: s_endpgm @@ -1930,8 +1990,8 @@ entry: define amdgpu_kernel void @sub_i32_varying_offset(ptr addrspace(1) %out, ptr addrspace(8) %inout) { ; GFX6-LABEL: sub_i32_varying_offset: ; GFX6: ; %bb.0: ; %entry -; GFX6-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0xd -; GFX6-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9 +; GFX6-NEXT: s_load_dwordx4 s[4:7], s[2:3], 0xd +; GFX6-NEXT: s_load_dwordx2 s[0:1], s[2:3], 0x9 ; GFX6-NEXT: v_mov_b32_e32 v1, 1 ; GFX6-NEXT: s_waitcnt lgkmcnt(0) ; GFX6-NEXT: buffer_atomic_sub v1, v0, s[4:7], 0 offen glc @@ -1943,9 +2003,9 @@ define amdgpu_kernel void @sub_i32_varying_offset(ptr addrspace(1) %out, ptr add ; ; GFX8-LABEL: sub_i32_varying_offset: ; GFX8: ; %bb.0: ; %entry -; GFX8-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x34 +; GFX8-NEXT: s_load_dwordx4 s[4:7], s[2:3], 0x34 +; GFX8-NEXT: s_load_dwordx2 s[0:1], s[2:3], 0x24 ; GFX8-NEXT: v_mov_b32_e32 v2, 1 -; GFX8-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 ; GFX8-NEXT: s_waitcnt lgkmcnt(0) ; GFX8-NEXT: buffer_atomic_sub v2, v0, s[4:7], 0 offen glc ; GFX8-NEXT: v_mov_b32_e32 v0, s0 @@ -1956,9 +2016,9 @@ define amdgpu_kernel void @sub_i32_varying_offset(ptr addrspace(1) %out, ptr add ; ; GFX9-LABEL: sub_i32_varying_offset: ; GFX9: ; %bb.0: ; %entry -; GFX9-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x34 +; GFX9-NEXT: s_load_dwordx4 s[4:7], s[2:3], 0x34 +; GFX9-NEXT: s_load_dwordx2 s[0:1], s[2:3], 0x24 ; GFX9-NEXT: v_mov_b32_e32 v1, 1 -; GFX9-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 ; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: buffer_atomic_sub v1, v0, s[4:7], 0 offen glc ; GFX9-NEXT: v_mov_b32_e32 v0, 0 @@ -1968,9 +2028,10 @@ define amdgpu_kernel void @sub_i32_varying_offset(ptr addrspace(1) %out, ptr add ; ; GFX10-LABEL: sub_i32_varying_offset: ; GFX10: ; %bb.0: ; %entry -; GFX10-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x34 +; GFX10-NEXT: s_clause 0x1 +; GFX10-NEXT: s_load_dwordx4 s[4:7], s[2:3], 0x34 +; GFX10-NEXT: s_load_dwordx2 s[0:1], s[2:3], 0x24 ; GFX10-NEXT: v_mov_b32_e32 v1, 1 -; GFX10-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 ; GFX10-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-NEXT: buffer_atomic_sub v1, v0, s[4:7], 0 offen glc ; GFX10-NEXT: v_mov_b32_e32 v0, 0 @@ -1978,36 +2039,73 @@ define amdgpu_kernel void @sub_i32_varying_offset(ptr addrspace(1) %out, ptr add ; GFX10-NEXT: global_store_dword v0, v1, s[0:1] ; GFX10-NEXT: s_endpgm ; -; GFX11-LABEL: sub_i32_varying_offset: -; GFX11: ; %bb.0: ; %entry -; GFX11-NEXT: s_load_b128 s[4:7], s[0:1], 0x34 -; GFX11-NEXT: v_mov_b32_e32 v1, 1 -; GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x24 -; GFX11-NEXT: s_waitcnt lgkmcnt(0) -; GFX11-NEXT: buffer_atomic_sub_u32 v1, v0, s[4:7], 0 offen glc -; GFX11-NEXT: v_mov_b32_e32 v0, 0 -; GFX11-NEXT: s_waitcnt vmcnt(0) -; GFX11-NEXT: global_store_b32 v0, v1, s[0:1] -; GFX11-NEXT: s_nop 0 -; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) -; GFX11-NEXT: s_endpgm +; GFX11W64-LABEL: sub_i32_varying_offset: +; GFX11W64: ; %bb.0: ; %entry +; GFX11W64-NEXT: s_clause 0x1 +; GFX11W64-NEXT: s_load_b128 s[4:7], s[2:3], 0x34 +; GFX11W64-NEXT: s_load_b64 s[0:1], s[2:3], 0x24 +; GFX11W64-NEXT: v_and_b32_e32 v0, 0x3ff, v0 +; GFX11W64-NEXT: v_mov_b32_e32 v1, 1 +; GFX11W64-NEXT: s_waitcnt lgkmcnt(0) +; GFX11W64-NEXT: buffer_atomic_sub_u32 v1, v0, s[4:7], 0 offen glc +; GFX11W64-NEXT: v_mov_b32_e32 v0, 0 +; GFX11W64-NEXT: s_waitcnt vmcnt(0) +; GFX11W64-NEXT: global_store_b32 v0, v1, s[0:1] +; GFX11W64-NEXT: s_nop 0 +; GFX11W64-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GFX11W64-NEXT: s_endpgm ; -; GFX12-LABEL: sub_i32_varying_offset: -; GFX12: ; %bb.0: ; %entry -; GFX12-NEXT: s_load_b128 s[4:7], s[0:1], 0x34 -; GFX12-NEXT: v_mov_b32_e32 v1, 1 -; GFX12-NEXT: s_load_b64 s[0:1], s[0:1], 0x24 -; GFX12-NEXT: s_wait_kmcnt 0x0 -; GFX12-NEXT: buffer_atomic_sub_u32 v1, v0, s[4:7], null offen th:TH_ATOMIC_RETURN -; GFX12-NEXT: v_mov_b32_e32 v0, 0 -; GFX12-NEXT: s_wait_loadcnt 0x0 -; GFX12-NEXT: global_store_b32 v0, v1, s[0:1] -; GFX12-NEXT: s_nop 0 -; GFX12-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) -; GFX12-NEXT: s_endpgm +; GFX11W32-LABEL: sub_i32_varying_offset: +; GFX11W32: ; %bb.0: ; %entry +; GFX11W32-NEXT: s_clause 0x1 +; GFX11W32-NEXT: s_load_b128 s[4:7], s[2:3], 0x34 +; GFX11W32-NEXT: s_load_b64 s[0:1], s[2:3], 0x24 +; GFX11W32-NEXT: v_dual_mov_b32 v1, 1 :: v_dual_and_b32 v0, 0x3ff, v0 +; GFX11W32-NEXT: s_waitcnt lgkmcnt(0) +; GFX11W32-NEXT: buffer_atomic_sub_u32 v1, v0, s[4:7], 0 offen glc +; GFX11W32-NEXT: v_mov_b32_e32 v0, 0 +; GFX11W32-NEXT: s_waitcnt vmcnt(0) +; GFX11W32-NEXT: global_store_b32 v0, v1, s[0:1] +; GFX11W32-NEXT: s_nop 0 +; GFX11W32-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GFX11W32-NEXT: s_endpgm +; +; GFX12W64-LABEL: sub_i32_varying_offset: +; GFX12W64: ; %bb.0: ; %entry +; GFX12W64-NEXT: s_clause 0x1 +; GFX12W64-NEXT: s_load_b128 s[4:7], s[2:3], 0x34 +; GFX12W64-NEXT: s_load_b64 s[0:1], s[2:3], 0x24 +; GFX12W64-NEXT: v_and_b32_e32 v0, 0x3ff, v0 +; GFX12W64-NEXT: v_mov_b32_e32 v1, 1 +; GFX12W64-NEXT: s_wait_kmcnt 0x0 +; GFX12W64-NEXT: buffer_atomic_sub_u32 v1, v0, s[4:7], null offen th:TH_ATOMIC_RETURN +; GFX12W64-NEXT: v_mov_b32_e32 v0, 0 +; GFX12W64-NEXT: s_wait_loadcnt 0x0 +; GFX12W64-NEXT: global_store_b32 v0, v1, s[0:1] +; GFX12W64-NEXT: s_nop 0 +; GFX12W64-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GFX12W64-NEXT: s_endpgm +; +; GFX12W32-LABEL: sub_i32_varying_offset: +; GFX12W32: ; %bb.0: ; %entry +; GFX12W32-NEXT: s_clause 0x1 +; GFX12W32-NEXT: s_load_b128 s[4:7], s[2:3], 0x34 +; GFX12W32-NEXT: s_load_b64 s[0:1], s[2:3], 0x24 +; GFX12W32-NEXT: v_dual_mov_b32 v1, 1 :: v_dual_and_b32 v0, 0x3ff, v0 +; GFX12W32-NEXT: s_wait_kmcnt 0x0 +; GFX12W32-NEXT: buffer_atomic_sub_u32 v1, v0, s[4:7], null offen th:TH_ATOMIC_RETURN +; GFX12W32-NEXT: v_mov_b32_e32 v0, 0 +; GFX12W32-NEXT: s_wait_loadcnt 0x0 +; GFX12W32-NEXT: global_store_b32 v0, v1, s[0:1] +; GFX12W32-NEXT: s_nop 0 +; GFX12W32-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GFX12W32-NEXT: s_endpgm entry: %lane = call i32 @llvm.amdgcn.workitem.id.x() %old = call i32 @llvm.amdgcn.raw.ptr.buffer.atomic.sub(i32 1, ptr addrspace(8) %inout, i32 %lane, i32 0, i32 0) store i32 %old, ptr addrspace(1) %out ret void } +;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line: +; GFX11: {{.*}} +; GFX12: {{.*}} |