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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2024-07-14 08:36:33 +0400 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2024-07-14 08:36:33 +0400 |
| commit | 78bc1b64a6dc3fb6191355a5e1b502be8b3668e7 (patch) | |
| tree | 3ba6a6d7eb6a3513d59bd5b8b0e09aa458e101f3 /llvm/test/CodeGen/MIR/AMDGPU/machine-function-info.ll | |
| parent | 78266ab0dc64dbc208035acc455f1b8ef22af387 (diff) | |
AMDGPU: Move attributor into optimization pipeline (#83131)
Removing it from the codegen pipeline induces a lot of test churn
because llc is no longer optimizing out implicit arguments to kernels.
Mostly mechanical, but there are some creative test updates. I preferred
to take the changes as-is in tests where the ABI isn't relevant. In
cases where it's more relevant, or the optimize out logic was too
ingrained in the test, I pre-run the optimization. Some cases manually
add attributes to disable inputs.
Diffstat (limited to 'llvm/test/CodeGen/MIR/AMDGPU/machine-function-info.ll')
| -rw-r--r-- | llvm/test/CodeGen/MIR/AMDGPU/machine-function-info.ll | 12 |
1 files changed, 9 insertions, 3 deletions
diff --git a/llvm/test/CodeGen/MIR/AMDGPU/machine-function-info.ll b/llvm/test/CodeGen/MIR/AMDGPU/machine-function-info.ll index 8326d95e0e7f..b3ed7376a1ed 100644 --- a/llvm/test/CodeGen/MIR/AMDGPU/machine-function-info.ll +++ b/llvm/test/CodeGen/MIR/AMDGPU/machine-function-info.ll @@ -27,10 +27,16 @@ ; CHECK-NEXT: returnsVoid: true ; CHECK-NEXT: argumentInfo: ; CHECK-NEXT: privateSegmentBuffer: { reg: '$sgpr0_sgpr1_sgpr2_sgpr3' } -; CHECK-NEXT: kernargSegmentPtr: { reg: '$sgpr4_sgpr5' } -; CHECK-NEXT: workGroupIDX: { reg: '$sgpr6' } -; CHECK-NEXT: privateSegmentWaveByteOffset: { reg: '$sgpr7' } +; CHECK-NEXT: dispatchPtr: { reg: '$sgpr4_sgpr5' } +; CHECK-NEXT: kernargSegmentPtr: { reg: '$sgpr6_sgpr7' } +; CHECK-NEXT: dispatchID: { reg: '$sgpr8_sgpr9' } +; CHECK-NEXT: workGroupIDX: { reg: '$sgpr10' } +; CHECK-NEXT: workGroupIDY: { reg: '$sgpr11' } +; CHECK-NEXT: workGroupIDZ: { reg: '$sgpr12' } +; CHECK-NEXT: privateSegmentWaveByteOffset: { reg: '$sgpr13' } ; CHECK-NEXT: workItemIDX: { reg: '$vgpr0' } +; CHECK-NEXT: workItemIDY: { reg: '$vgpr1' } +; CHECK-NEXT: workItemIDZ: { reg: '$vgpr2' } ; CHECK-NEXT: psInputAddr: 0 ; CHECK-NEXT: psInputEnable: 0 ; CHECK-NEXT: mode: |