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authorDavid Spickett <david.spickett@linaro.org>2020-05-06 13:19:52 +0100
committerDavid Spickett <david.spickett@linaro.org>2020-05-06 13:40:49 +0100
commit055ea585c77cd8ae9cd3bc327c1e4404020fdf27 (patch)
treed7e66a981832497d318d2c437d1a85a2110df4b7 /llvm/lib/CodeGen/CallingConvLower.cpp
parentdee4cbcd479f075ae33a8d3841fedde388c45782 (diff)
Reland "[CodeGen] Make logic of CCState::resultsCompatible clearer"
This relands commit d782d1f898eaafee49548d5332e84c3ae11ebac4. With a typo fixed, which was causing the x86 test failure.
Diffstat (limited to 'llvm/lib/CodeGen/CallingConvLower.cpp')
-rw-r--r--llvm/lib/CodeGen/CallingConvLower.cpp18
1 files changed, 7 insertions, 11 deletions
diff --git a/llvm/lib/CodeGen/CallingConvLower.cpp b/llvm/lib/CodeGen/CallingConvLower.cpp
index 12c4f1b6a219..bc7fa21b8020 100644
--- a/llvm/lib/CodeGen/CallingConvLower.cpp
+++ b/llvm/lib/CodeGen/CallingConvLower.cpp
@@ -276,18 +276,14 @@ bool CCState::resultsCompatible(CallingConv::ID CalleeCC,
for (unsigned I = 0, E = RVLocs1.size(); I != E; ++I) {
const CCValAssign &Loc1 = RVLocs1[I];
const CCValAssign &Loc2 = RVLocs2[I];
- if (Loc1.getLocInfo() != Loc2.getLocInfo())
- return false;
- bool RegLoc1 = Loc1.isRegLoc();
- if (RegLoc1 != Loc2.isRegLoc())
+
+ if ( // Must both be in registers, or both in memory
+ Loc1.isRegLoc() != Loc2.isRegLoc() ||
+ // Must fill the same part of their locations
+ Loc1.getLocInfo() != Loc2.getLocInfo() ||
+ // Memory offset/register number must be the same
+ Loc1.getExtraInfo() != Loc2.getExtraInfo())
return false;
- if (RegLoc1) {
- if (Loc1.getLocReg() != Loc2.getLocReg())
- return false;
- } else {
- if (Loc1.getLocMemOffset() != Loc2.getLocMemOffset())
- return false;
- }
}
return true;
}